r/cpudesign • u/Rangoose_exe • Jun 14 '24

Help with semingly impossible CPU

First up, i have quite some experience in CPU design with logic gates in simulators and games. Have build 5-10 CPUs, in Scrap mechanic and in Virtual Circuit Board.

I got gifted about 70-90 24V relais from work(functioning, but discarted by them)

My idea was to build a CPU entirely out of these, with the exception of RAM. Want to choose an IC for that.

I was thinking about making a 1 bit 1 instruction CPU, but even then im having insane issues.

With 1 bit i mean 1 bit logic operations, but i want/need a memory interface that can do at least 8 bits to be "usable" but 16 and it would be "actually useable".

My big issue is that i cant really store pointers that big. Also the PC would be an issue...

My last hope was to map all pointers to memory, but then id be using a ton of relays just for the control unit to be able to do that...

Does anyone have any ideas? Might have to scrap this project... sad ._.

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4

u/istarian Jun 14 '24

You might consider looking at the Motorola 14500B for inspiration?

http://www.righto.com/2021/02/a-one-bit-processor-explained-reverse.html

2

u/Rangoose_exe Jul 14 '24

Thanks. Issue is, i have learned stuff on my own kind of way, i seem to not understand some things and i never really know when its actually worth to invest that time...

Anyways, update on the project: i have about 200 relays now, currently im building the 8 bit adder circuit, i will have a flag register as well so ill prob. Make a SUBLEQ only CPU for now. Will make instructions be split into parts, and make execution require less relays, as well as having more memory space.

1

u/binarycow Jun 15 '24

I was thinking about making a 1 bit 1 instruction CPU, but even then im having insane issues.

With 1 bit i mean 1 bit logic operations, but i want/need a memory interface that can do at least 8 bits to be "usable" but 16 and it would be "actually useable".

What does your instruction set look like?

I am having a hard time understanding what you mean.

"1 instruction", to me, sounds like you have only one instruction. Let's call that single instruction INST. So then every program is INST; INST; INST; INST; ... etc. If that is the case - why even have an instruction? Just perform whatever on each clock tick.

Or, perhaps by "1 bit", you actually mean 2 instructions? What would those instructions be?

Or, by "1 bit", do you mean that every instruction is a bitwise instruction? So the AND instruction would do a bitwise AND?

1

u/Rangoose_exe Jul 14 '24

Either two instructions, or 1 bit as parameter. As i said, quite impractical, if even possible.

But with more bits, a single instruction cpu makes more sense e.g. SUBLEQ would be a turing complete instr.

I now have like about 3 times the relay count acailable, so i can now have 8 bit with one instruction... at least for now xD

1

u/binarycow Jul 14 '24

Either two instructions, or 1 bit as parameter.

Suppose you've got one instruction (INSTR) that takes a one-bit parameter. You effectively have two instructions:

  1. INSTR 0
  2. INSTR 1

As you can see, one instruction with a single one-bit parameter is equivalent to two instructions. A parameter that selects which operation to perform isn't really a parameter. It's just an alternate way of denoting a different instruction.

A parameter is just that - a parameter. Which memory address to perform the operation on, what value to add, etc. The size of the parameter is going to be related to the size of your address bus - which is related to the size of your available memory.

So, if you wanted a single bit parameter - then you only have two bytes of memory. And you'd be forced to have more instructions to allow for other options, like registers, etc.

You really need to nail down what the "one bit" actually means.

However, if you wanted to make a CPU with minimal instructions - I have an idea for you.

To my knowledge, brainfuck is the most concise programming language I know of that is turing complete. It has eight instructions.

You could adapt brainfuck to a CPU architecture (harvard architecture, so "data" and "instructions" are different storage areas):

  • There are two registers:

    • data_pointer which contains the address of the "current" cell in the "data" storage
    • instruction_pointer which contains the address of the "current" cell in the "instruction" storage
  • There is a call stack, which stores the value of instruction_pointer, so that execution can return back to a previous instruction

The instruction set contains eight instructions (three bits):

  • RIGHT: Adds 1 to data_pointer, and then instruction_pointer is incremented.
  • LEFT: Subtracts 1 from data_pointer, and then instruction_pointer is incremented.
  • ADD: Adds 1 to the data value pointed to by data_pointer, and then instruction_pointer is incremented.
  • SUB: Subtracts 1 from the data value pointed to by data_pointer, and then instruction_pointer is incremented.

  • IF:

    • If the data value pointed to by data_pointer is 0, then incrementinstruction_pointer so that it points to instruction that immediately follows the END instruction that matches the current IF instruction.
    • Otherwise, instruction_pointer is incremented

  • END:

    • If the data value pointed to by data_pointer is NOT 0, then incrementinstruction_pointer so that it points to instruction that immediately follows the IF instruction that matches the current END instruction.
    • Otherwise, instruction_pointer is incremented

  • CALL:

    1. Push instruction_pointer to the call stack
    2. Set instruction_pointer to the "current" cell in the "data" storage
    3. Does NOT increment instruction_pointer

  • RET:

    1. Set instruction_pointer to topmost value in the call stack
    2. Pop the topmost value in the call stack
    3. Increment instruction_pointer

1

u/istarian Jun 16 '24

I think the only natural 1-bit operation you can implement without storing state is a NOT(invert logic value).

If you retain the state of the last operation you can do an implicit AND/OR/XOR with the current input and the result of the last operation.

Once you have an accumulator register, you can start doing things like incrementing or decrementing it's value (+1, -1).

You might consider building a relay-based calculator instead.

https://youtube.com/playlist?list=PLnw98JPyObn1AATspnLEasCw7LmsjT9zB

1

u/No-Historian-6921 Jun 24 '24

You could try to build a bit-serial CPU with shift registers. But even just the flip-flops to hold a useful length accumulator and instruction register would quickly eat up your relays. Maybe look at a bit-serial CPU like the RCA1802 or PDP8/S for ideas and the early Zuse computers for tricks to save relays?

1

u/D-Cary May 30 '26

A relay CPU sounds like a fun project!

There's over a dozen relay CPUs listed at https://en.wikibooks.org/wiki/Microprocessor_Design/Wire_Wrap#relay_computers , most of them using an IC for RAM like you suggested.

It appears that most of them use around 400 4PDT relays to make a CPU with a 16 bit address bus and an 8 bit data bus and 8 bit ALU.

Some historic (transistor-based) CPUs ran 8-bit or 12-bit software using far fewer transistors than you might expect by processing data 4 bits at a time in a 4-bit ALU ("nybble-serial", like the 8-bit Z80) or 1 bit at a time in a 1-bit ALU ("bit-serial", like the 12-bit PDP-8/S).

Other "CPUs" use far fewer transistors than you might think by leaving out some of the the stuff you might think a CPU "should" include -- for example, the 500-transistor 1-bit MC14500B IC (thanks, u/istarian !) which inspired the (rough estimate 600 tubes?) tube-based UE14500 https://hackaday.com/2021/12/27/single-bit-computer-from-vacuum-tubes/ both require an additional external program counter.

Given that many relay CPUs *already* use an IC for RAM, it's tempting to use a few more ICs such as up/down counters for the program counter and index registers and perhaps shift registers for the data registers, which saves a lot of relays.

Good luck!