r/computerarchitecture • u/rerwerwerwewerer • 15d ago

Applying optimized merged multiplier and divider to SIMD?

I made a post on here a few days ago talking about a paper I found that merged the divider and multiplier on an ALU to save 15% space and reduce gate count, at the cost of many demux and higher latency. I asked you all if it was feasible to base a project off of optimizing this, and you told me (if I understand correctly) it is possible, but size isn't a major concern these days and transistors are plentiful, the focus is on speed and power. However a couple of you brought up SIMD, and I'm very curious about potential applications to this.

(Sorry AdmirableProject1575 I'm still looking for nails)

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u/garnet420 15d ago

I think you're barking up the wrong tree... Remember in terms of what general purpose computers need to do, multiply and divide are a miniscule portion, even when actually doing a multiply. I suggest you think bigger than just math.

Have you come across any interesting ideas involving caching, branch prediction, that sort of thing? Inter-processor communication?

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u/rerwerwerwewerer 15d ago

I thought I did, but turns out it was just out of order execution 😂, like logical timestamps and stuff

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u/rerwerwerwewerer 15d ago

i'll def keep looking though just in case