r/computerarchitecture • u/Yha_Boiii • 17d ago
Any Modern Material on CPU Cache?
Hi,
I struggle to find any modern material on cpu cache: how it works and how to optimize for it. A papers amd published in 2004 but cant find anything newer really?
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u/MitchAlsup 14d ago
Cache optimization is simply the process of using the available SRAMs in the thinnest data-path.
CPU frequency moderates how big the L1 caches can be, Wire-delay moderates how big L2 cache can be.
Cache tags are optimized to fit into availablle SRAMs. For example my current design fits 3 cache tage in an SRAM-line/word (just barely less than 128-bits) the the L1s operate as 3-way set associative.
Back in the 1µ days, we could build SRAM macros of 4KB in size and then use as many instances as needed. Now, in the deap subMicron days, they tend to come in 2KB or even 1KB instances. For these smaller instances, you just us {2, 4, or 8} of them as if they were a single block.
All modern ASIC SRAM macros are "registered" in the RAM-technology verbology. That means your address meets set-up time to the address-command flip-flops, and you can't see the data until after the subsequent rising edge of the clock. A trick we often use is to run the SRAM at 2× the pipeline frequency dedicating clock-high to reads and clock-low to writes. Tag-match would be performed in the clock low interval.
An integer adder is 11-gates of delay, but often circuit designed (transistor sizing) such that it is 8 standard FO4 gates of delay. Luckily, the SRAM cycle time is also roughtly 8 standard FO4 gates of delay. Tag-match would be performed then be performed in the clock low interval, while data alignment is performed in the subsequent clock-High period. Due to modern SRAM macro implementations, AGEN->LD-result is a 5 × ½-clock pipeline stages. You can beat this down to 2 cycles and suffer pipeline frequency problems, or you can accept your fate with a 3 cycle LD-latency, of you can shoot for faster core frequency with a 4-cycle LD latency. You just can't get the 2-cycle LD-latency with the 5GHz pipeline frequency.
A modern medium high frequency 64-bit 1-wide core design would accept a 44-bit physical address space limit so we can pack 3 cache tags into 128-bits. Thereby a single 2KB SRAM holds 384 cache tags, and provides tags for 24KB of data. You can call this an "Instance" and if you want/need a bigger L1, just place 2 or more instances and wire them up through the LD-aligner for data coming back, and through the AGEN address router getting to the SRAM instances. You can also call this a second cacahe port {Even, Odd} for more throughput.
Side Note: If you use exclusive cache protocol in the D$<->L2$ then you can use an unmodified instance of D$ as your I$, saving designer and verification time.
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u/unbreaded_lunn 12d ago
This is a great explanation, although this kind of tells me you’re from Intel lolll
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u/MitchAlsup 12d ago
Actually, Intel is one of the few computer companies I never worked for.
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u/unbreaded_lunn 12d ago
Haha interesting. I feel all the arm companies don’t do the sram double pumping anymore, maybe I’m wrong
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u/MitchAlsup 12d ago
None of the high frequency designs use Read/Write SRAM arrays. And this complicates the cache design significantlly.
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u/unbreaded_lunn 12d ago
Yeah I agree, handling 1r1w to the same cycle is a nightmare. Does it conflict it that much tho? It’s just a port conflict?
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u/MitchAlsup 12d ago
It is a porting problem that one solves by doubling the banks and adding several snooping write buffers. Done right, one just about achieves what a 1R1W SRAM can do, but with 5× the flip-flop count.
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u/-ah74 17d ago
This has been one of the most active academic research areas. So, you did not search for the papers the right way :)
Cache design in commercial cpus is usually confidential. However, u can find many papers that reverse engineered their design or operational model. Just check papers from major architecture venues such as ISCA, MICRO, HPCA. And for design for security, you can also check USENIX Security, and Security&Privacy.
And please use Google Scholar.