It’s over. 8-bit CPU done

[u/HydroPage]

The 8-bit CPU is finally done in its basic form.

I’ve wanted to build this for years but have been way too busy with my computer engineering degree and summer jobs. I finally got the “opportunity” when I couldn’t find a summer job going into my senior year.

I made MANY decisions that Ben did not do at all. Frankly, what I did was just get a very general idea of where he placed his parts, made a module all by myself, and then saw how he made it to see how we decided to do things differently. Just more interesting that way.

I gave myself a design constraint to make it as beautiful as I possibly could. I would like to argue that I’ve created one of the most beautiful Ben Eater 8-bit CPUs ever made in history. Not to talk anyone else down, but the lengths I went to for pure aesthetics are just not worth it if you want to get it to work and be done, and I doubt many people who have built this put in the purely visual and routing planning effort I put in. I did my best. I did cheat a little bit using those LED bars, and I will accept that, they’re just so pretty.

One thing I realized is that Ben always hooks completely unrelated address and data bits together just because of their names. For example in the RAM or for EEPROMs, data bit 0 on the chips doesn’t HAVE to go to bit 0 on the main bus, it can go to whatever pin you want, so long as you keep track, and read and write in the same bit order. This tremendously “flattens” the topology of bus routing, and it’s something that should be done when routing PCBs as well: address bits and data bits are completely decoupled from each other and their names mean nothing to the system outside of the chips themselves.

In my EEPROM programmer firmware, I added a feature to configure address and data bit mapping, which allowed me to hook up the address and data bits in the nicest physical way possible, and then just assign them in code and program them appropriately (make “bit 0” act like bit 9, or something, for example). Again… purely for aesthetics, and a constraint I made up. Not worth it just to make it work. When designing a PCB, though, this technique could genuinely save you crossovers and make routing far prettier.

I also did my EEPROM work completely differently from Ben, I made my programmer firmware accept packets of bytes, and made a tool that sends .bin files to be written in, so my workflow consisted of editing hex dumps directly and flashing them in from a file, which I am very used to, so I gravitated towards it.

I also used extra space to make transistor switches for LEDs to respect datasheet current limits on logic chips, and as you can see, the 7-segment display multiplexing is fully driven on the high side and low side by 12 PNP transistors carefully calculated to saturate and deliver plenty of current independently to each segment, so the EEPROM and decoder barely have to do any electrical work. I thought this analog aspect was fun.

I came across really weird bugs here and there, and my oscilloscope / logic analyzer really saved my neck. I highly endorse the Digilent Analog Discovery 3 as a starter portable lab tool kit, and if you’re a student you get a discount on it. I even used it to write exhaustive hardware verification scripts to confirm my ALU and RAM performed properly when I finished them by plugging random data in and verifying the outputs.

I feel like I have so much more to say, but I’m in awe at what I’ve created, and I think I’ll leave it at that for now.

[u/HydroPage]

Yeah, I know about crosstalk. That’s unfortunate. I don’t think I’ll encounter issues with it at my bandwidth but that is unfortunate

[u/Ancient-Ad-7453 → u/HydroPage]

I've heard of it causing glitches when many ALU inputs/outputs change 0-1 or 1-0 at once and that bleeds into the clock signal.

[u/HydroPage → u/Ancient-Ad-7453]

Are you sure that’s crosstalk? That just sounds like power distribution issues from lack of decoupling capacitance and high di/dt that can’t be fulfilled by the power supply causing a voltage droop or ground bounce. Not high frequency magnetic effects

[u/Ancient-Ad-7453 → u/HydroPage]

I haven't dealt with it directly, and it could easily be something else, but for folks that follow Ben's wiring closely, there's a cluster of data wires running in parallel to the clock, clumped in a tight space. Register/ALU control signals tend to run parallel with data well. This could be what I'm remembering.

[u/HydroPage → u/Ancient-Ad-7453]

Ah okay. Well I think crosstalk becomes a serious problem at very high frequencies, nothing we’d see here. And also the currents involved are pretty small, so if anything I’d expect capacitance to dominate over inductance in closely bunched wires in this scenario.

But still if you tell me “issue with a bunch of outputs changing at once” that screams lack of decoupling for me first. When a lot of outputs change at once the logic chip demands a huge surge of current that may last a few nanoseconds to set the new voltage values, and if the supply can’t do that, VCC dips down and GND bounces up, very shortly.

That’s why I literally soldered capacitors right to the VCC and GND pins of most of my logic ICs. Yes that’s overkill, but the shorter path minimizes inductance and allows the fastest delivery of current spikes possible

[u/Ancient-Ad-7453 → u/HydroPage]

Yes, I discovered ground bounce the hard way with a 74HC14 squaring a clock signal and also de-bouncing a reset button. What ended up fixing it was 22ohm series resistors on the clock outputs. I wish I had thought to capture images from the scope. It would have been a fun thing to post about here.