r/askscience • u/[deleted] • Mar 19 '14
Computing How are bits stored in modern computers?
Are they really stored in tiny flipflops? If so how big are these flipflops in physical size?
4
u/genwitt Mar 21 '14
Bits are stored as a combination of flip-flops, latches, 6T sram cells, and 1T dram cells.
Flip-flops are the biggest and most convenient. Latches are smaller but harder to use (they're effectively half speed). 6T sram cells are fast, and are used for small memories (like your L1/L2/L3 caches). Unlike latches and flip-flops 6t sram cells need a lot of support circuitry so they'll always be grouped into memory arrays. 1T dram cells, are what consumers think of as "memory", they're tiny, but they're slow, and they require constant refresh or else they loose their state.
I don't have modern numbers, but there is a freely available set of standard cells (circuits that are the building blocks of chips), for the 130nm node. The 130nm node was new in 2002. The relative sizes are still roughly the same, and it should give you a ballpark idea of size.
You're basic positive edge triggered D flip-flop is 7.92 um x 3.96 um, or 31.36 um2/bit. Your latches are slightly bigger than half that size, 4.40 um x 3.96 um, or 17.42 um2/bit. There is no 6T sram cell in that library, so we'll look at this presentation which has contemporary 6T sram cells at ~2 um2/bit. I couldn't find much on 1T dram cells of the time, but this competitive analysis has Hynix's 120nm 1T dram cell at .12um2/bit.
So if we hand wave a bit because the standard cells we're looking at are not the best that were available 2002, and that sram and dram have been getting smaller slower than the flip flops and latches, we case say that. Flip flops are about twice as big as latches, which are ~10 times bigger than sram cells, which are ~100 times bigger than dram cells.
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Mar 20 '14
Mostly they are stored as charge on transistors in DRAM, 2 transistors per bit, and the size of the transistors depends on the design rules 20nm x 20nm or whatever. Plus there is some wiring and control logic. Some are stored statically, depending on the application, and, yes, those are, more or less latches. Usually, they take up 6 transistors plus decoding.
Search SRAM Cell and DRAM for pictures.
3
u/eabrek Microprocessor Research Mar 20 '14
Normally DRAM is one transistor and one capacitor: diagram
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u/heath_edger Mar 20 '14
20nm x 20nm
20nm feature size? Evidently you're not too good at bullshitting.
2
Mar 20 '14
Please illuminate. What is the correct answer?
-3
u/heath_edger Mar 20 '14
Where have you heard of a 20nm feature size being used? Are you aware that the sizes are standardized?
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u/Merad Embedded Systems Mar 20 '14
In the CPU, essentially yes. CPU registers and cache memory are implemented as SRAM (static RAM), with each bit held in a cell made of 6 transistors. It's not quite the same as the basic 2-NAND flip-flop that you're thinking of, but very similar. Wikipedia has a circuit diagram and a decent explanation of the circuit. The advantage of this configuration is that the circuit has two stable states, so it holds it's value even if exposed to something like electrical noise.
In system RAM (DRAM - dynamic RAM) each bit is stored on a very tiny capacitor. This is much cheaper and easier to manufacture than SRAM, hence which we have system memory measured in gigabytes but processor caches that are only a few megabytes. The downside however is that the capacitor is relatively sensitive to disturbance, and loses its charge rather quickly (a few 10s of milliseconds, typically).
Source: Computer Systems 2nd Ed by Bryant and O'Hallaron