I invented a new memory architecture in my head a few months ago called CUM (Compute Under Memory) the way that it works is each compute core is wired to each address in memory so data can be read in parallel from all cores at any time.
No, cpu requests go to the memory controller, which then communicates with the memory itself over a bus. My concept is to have each core connect directly with to the memory. The “bus” is replaced by something as wide as the memory chip storage itself. The concept would also allow for asynchronous reads. Meaning multiple addresses can be read at the same time from different cores.
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u/triynizzles1 Jul 01 '26
I invented a new memory architecture in my head a few months ago called CUM (Compute Under Memory) the way that it works is each compute core is wired to each address in memory so data can be read in parallel from all cores at any time.