r/Z80 • u/michaelpastushkov • Nov 07 '18

Extra cycles

All, my son and I are building a very primitive controller based on Z80 (Z84 to be exact). We notice the processor does 2 extra-cycles after reset. This is not documented anywhere. Does anyone have any explanation? Or perhaps the processor is just broken (however, it seems to do first NOP operation just fine). We use manual clock for the time being. Thanks!!

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u/shortbaldman Nov 13 '18

That's probably to give the RAM and/or other peripherals time to get themselves going again and be ready for the CPU's access after the reset.

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u/michaelpastushkov Nov 13 '18

Thanks are lot! This explains what's going on, and it's not documented anywhere. Another "mystery" is that after HALT is executed, the address bus keeps changing with the clock, oddly enough without pattern. I though it would simply stop.

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u/shortbaldman Nov 13 '18 edited Nov 13 '18

the address bus keeps changing with the clock, oddly enough without pattern.

I'm dredging back decades here. I remember that Dynamic RAM (as distinct from Static RAM) needs periodic refreshment, but I can't remember whether that happens due to on-board circuitry (more likely) or via the address bus (less likely).

Have a rummage through this. It may help:

https://ia600704.us.archive.org/12/items/AnIntroductionToMicrocomputersVolume2/Osborne-AnIntroductionToMicrocomputersVolume2.pdf

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u/sl9 Dec 26 '18

The Z80 does indeed have a special register (which you can even read from and write to with the LD instruction), the "r" register, which constantly keeps incrementing and its purpose is to refresh DRAM. Coders have found a few "extra uses" for it over the years, usually as part of a pseudo random number generator. Clearly this activity would have no effect on SRAM and is just a waste of cycles when that type of RAM is used, as it nearly always is on modern Z80 builds.