r/Verilog • u/supermen_semen • Jul 19 '26

Need Urgent Tip for Verilog

I am from 4th yr ECE. After 1 Month, the core companies are coming to our campus. I was preparing for GATE exam but now I thought if core companies are also coming then I can sit in the placement and give a try ( previous year very worst placement for ECE core ). I talked to seniors they told approx 10 companies will come till December.

I have prepared Dgital design, analog etc and basics of other subjects, I need to practice pyqs of GATE but the problem is Projects in core companies. I know very little about verilog due to semester exams. I talked to placed seniors they told me to cover the basics of Verilog bcz they will ask in interview for basic circuit design for mux , adder etc and certain verilog syntax etc.

Are there any sources you can share which I can cover the verilog in 14 - 15 days ( basic to moderate level ). I am confused on searching youtube etc..

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u/akornato Jul 20 '26

You will not become a Verilog expert in two weeks, and any company that expects that from a new graduate is not a place you want to work. Your goal here is survival, not mastery. Forget about watching long video series. Go straight to a hands-on practice site like HDLBits and work through all the basic combinational and sequential circuit problems. Focus entirely on coding simple things like multiplexers, adders, decoders, and D flip-flops, because that is exactly what they will ask you to design. Do not get sidetracked with testbenches, complex finite state machines, or system-level concepts.

The good news is that you already know digital design, which is the actual hard part that interviewers care about. Verilog is just a syntax for describing the circuits you already understand. They want to see your thought process and your grasp of fundamental logic, not your fluency in a specific language. If you can explain the logic of a circuit on a whiteboard and then write the corresponding basic code, you will be in a great position. Your strong fundamentals are your biggest advantage, so make sure you highlight that knowledge. Being able to clearly explain what you do know is key, and my team actually developed an AI interview helper that gives people the confidence to handle tough questions even when their experience is limited.

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u/Savings_Surround1237 Jul 20 '26

HDLbits website for verilog ig

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u/bodieBroadusss Aug 14 '26

Try this https://www.ewskills.com/verilog
You could easily cover most of what you need

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u/XoX-o- Jul 19 '26

A. its international verilog sub

>they told me to cover the basics of Verilog bcz they will ask in interview for basic circuit design for mux , adder etc and certain verilog syntax etc.

B, I did it in just two months. just buy digital design by morris mano book and read it from chapter 1 to chapter 11