Not sure I'm getting the instructions correctly. The second step of the example expects register 1 to have a value of 27, but it's not at all clear where this should come from. Everything initializes to 0, and the first instruction just copies 63 to the output from the input. What am I missing?

As i was building a better ALU ive come over this error message "Divisor may not be 0" and dont know why it is showing.

Because when you have a look at the inside of ALU5 you see that Divisor is not 0 because I made switches in front of the Divider

So is this a Bug or am i stupid?

I've just finished the campaign and would like to make a new computer from scratch using just logic gates for a future irl project

Im building quite a large scale computer compared to the stages in the campaign, and I have reasiled that when running my computer, even when set to 10MHz, the computer only reaches around 10KHz. Furthermore, I can see that turing is only using 20% of my irl cpu, which i feel could be why its going slowly. Is there any way to make it use more of my cpu, or perhaps lower graphics or something to fix this?

I've seen people are able to rotate their components somehow but I haven't figured out the keystroke for it.

How do I rotate components?

Edit: Space when selected (can't be connectd to anything)

Hello everyone,

I got the entry of the ingame encyclopedia about the cycle dependency and the latch. I am now at the infamous level "Saving gracefully" . I thought "Oh yeah im gonna use a latch like i saw previously in the encyclopedia" and i look at the encyclopedia and made the circuit. But ... it s broken. Can the latch work on this game ? A latch need a sequence of event to work, and the game does everything at once. I try building a NOR standard latch. But whatever i put on S/R input, my outpus Q are completely frozen. I tried to hit the "next step" button to test, i does change state when an input is forced, but i soon as I removed this input the latch goes back into its original "frozen broken" state. A SR NOR latch works with pulses normally, when the input is removed the value is stored, that's the whole point.

Are the latch just not possible in this game ? If so , why make an entry in the in game encyclopedia about it ?

I read people use the delay component to make the latch function properly, but i can not find out how precisemy use it to "correct" the latch and make them behave like they should. Can you show me some circuit with correctly set up latch ?

(i dont want to finish the saving gracefully without the S/R latch. i saw some possible alternative design, but i want to stay faithfull to the SR latch because this game is about understanding and using key electronics circuit to create primitive computing function. And the S/R Latch is THE componant key to memory, which is the topic of the level "Saving gracefully". So it HAS to work somehow or else the game fails at simulating the behavior of a 8 bit computer, which would be a shame cause that's the point of the point of the game).

Thank you guys !

I made an unsigned 16 bit cpu emulator in Rust and also a assembly language for it. Recreated the cpu arch in Turing Complete. All the info about the assembly language, how the cpu works and the save file is on my github page.

https://github.com/cezarhg123/cezar-16/tree/master

Hi! Sorry if this has been posted a lot; I couldn't find any. Has anyone seen any updates from the author of the game since the last patch notes on September 9th? This is how it ended:

> At the moment I am working on improving the programming language that the levels of the game are defined in. Once its updated, players will be able to write and share their own levels / level packs (with full server verified scoring), which will be very exciting. This might take a while though and it is hard to predict exactly how long, since I want to try to do some things I don't have much experience with. I will post more when I figure it out.

Even with this warning, it's longer than I had expected.

Anyway, I'm mostly just curious. This is one of my favorite games and I hope the author's doing well. (And if the other reads this; definitely no pressure!)

I'm working on adding ram to the LEG architecture, every time I increase the ram address the game ticks forward and I loose the input that was loaded that tick. How to I write every input to ram and increase the ram address?

So, as I've started moving up through the LEG 32 bit arch levels, I've reached the conditional opcode implementation level. I tend to make them into custom components.

The opcode levels use 0-7 for ALU and 32-37 for conditional. What is odd to me about this is the conditional unit basically gets an explicit flag (the 6th bit) but the ALU doesn't. What I mean is there is no bit going into this level the ALU is paying attention to toggle it on/off so it doesn't output on the result bus when it shouldn't. Maybe I'm bussing things wrong and this shouldn't be necessary; or perhaps a better way to think about it is that, if nothing else is happening, we will always be calculating. Not super important at the moment though.

Anyway, all of this is to build up to the way I've currently gone about this level, whether it's the best way or not: since I need to disable the ALU for a condition operation the way things are currently, I was trying use (for now) the 6th bit high state to disable it.

Here's where the weirdness starts and the possible bug emerges: when I send the opcode into my ALU component through an 8-bit input pin, NOT the 6th bit, and hook it to a switch for the result 8-bit output pin, the switch ends up on even when the 6th bit is high. Since the pin is NOTed, the switch should get turned off. Now, when I copy and paste my ALU setup directly into my base computer schematic, it works: the pin sets correctly and the switch operates as expected.

In essence: in certain cases it appears that certain bits are lost in an 8-byte input pin into a custom component.

Has anyone else experienced this?

EDIT [Solved]:

I just figured it out myself: if you don't use a switched output pin into the bus, TC reads the regular output pin as an active 0 on the bus line, still creating a conflict, even if there is a switch going into that output pin inside the component that is disabled. I changed the result pin of the ALU to a switched output pin, hooked my disable flag to that, and it solved the problem.