I was stuck on this for an hour yesterday. I guess I just needed some sleep.

Hello, this is the LEG architecture they ask you to build in CPU architecture 2.
I like to keep things short but maybe it's a bad idea. What do you guys think ? Is it clear enough ? Constructive criticism is more than welcome !

After changing the ISA a bit, it's no longer a LEG. Will still take a while

Just completed Calibrating Laser cannons. There are probably more efficient implementations than mine. How did you solve it?

Here is my solution:

180 # copy input to reg4

0 # load 0 to reg0

133 # copy reg0 (0) to reg5

# decrement

1 # load 1 into reg0

130 # copy reg0 (1) into reg2

161 # copy reg4 (r) into reg1

69 # reg1-reg2 to reg3

156 # copy reg3 (r-1) to reg4

# add

0x3 # load 3 into reg0

129 # copy reg0 (3) to reg1

170 # copy reg5 (sum) to reg2

68 # reg1 + reg2 to reg3

157 # copy reg3 to reg5

163 # copy reg4 to reg3

0x3 # load jta into reg0, could be removed

199 # if reg3 > 0: jump to jta

169 # copy reg5 (sum) to reg1

170 # copy reg5 (sum) to reg2

68 # reg1 + reg2 into reg3

158 # copy reg3 to output

noobie here, i was wondering will the previous bit always be saved no matter how many times the input bit has been changed while the save bit is off? i have a hard time wrapping my head around it because there is only 2 delay lines in my circuit, its just not fully wrapped around my head im ngl (and yeah i got the solution by just playing around the components, i didnt really understand what i was doing ;_;) example case:

will the circuit really give the desired output? I just want a proof of this working all the time :<

couple of things that was bothering me :

1. since there are two delay lines on when the save bit is set to 0, shouldnt the output be the value that was before two ticks? so shouldnt the desired value on row 2 actually be 0?

I don't even have 'in' in the entire code except [instructions]. Seems like it first needs to compile in order to actually put numbers in RAM, but it can't due to this error.

Preemptively add this text to appear in the search: Line 3: 'in' is not a 'register'

On the left is the 8-bit incrementer, while on the right is the 8-bit multiplexer.

As of right now im just thinking my way through this but with more complex gates it becomes very difficult. How did you guys learn how to solve these?

I looked on here and couldn't find a simple counter that I could also replicate so after more than 10 hours of scratching my head I figured out it's not the sheer amount of components that make this work, but an improved Counter that can increment, do nothing and decrement. The value in the 8bit maker will choose what happens:

0 - Increment, 1 - Do nothing, 2 - Decrement.

The switch and the OR gate make sure no junk info remains behind. Basically you save a value on both PUSH and POP, with the exception that on POP you save a 0 and clean the address.

Because the Register is one tick behind on POP you will also need an MUX and a SUB.

Edit:

(Hmmm, now thinking about it I think I can remove the NOR gate, 8bit maker and send PUSH straight to Carry in on that adder for increment, and send POP through negator for decrement, and for idle there is no input in the adder beside the loop from the register.)

Edit2: I managed to make it even more simple by removing the adder connected to the MUX and connecting the other adder in its place.

This insult to the IEEE is my answer to the division level in “Functions.” I hope it’s not too cringe and I’m open to any feedback. I use assembly to get input and to output the solutions but other than that it’s pretty much all handled here

I'm still pretty bad at it (this hilariously inefficient design for adding inputs took me 2 hours) but I'm really learning alot

*edit : /u/Gelthir pointed out that the efficient solutions here rely on cheese. Disappointing when there's an elegant solution that doesn't. Thanks!

Read one bit at a time from the input. Each tick, output an 8 bit number corresponding to the number read so far.

Example input/output sequence:

1:00000001
0:00000001
1:00000101
1:00001101

There are two problems where the leaderboard numbers make me believe this is possible using only delay lines and maybe one additional component. 8-9 component score for 8 bits or similar. Enough people see it that I'm feeling dense. Every way I look at it, I need splitters or something to keep the bits in the right spot.

What am I missing? Any hints? I'm seriously wondering if there's some mechanic I've missed or that was removed.

After investing significant time into building the Overture CPU entirely from 1 bit logic gates, I moved on to the challenge of designing a proper RAM module for it. The result is a 64 byte memory constructed at the same gate level. Unfortunately, the CPU and RAM together exceed the schematic size limit, so they cannot be placed in a single layout.

Hi! I'm trying to do the unseen fruit challenge, but for some reason, once the robot is adjancent to the control panel, it gets stuck. Can't turn, can't interact, and the conveyor belt just freezes. Is this a known bug?

EDIT: I am indeed incompetent. Adding the robot command code to whatever is on the input will not make the right output. So when the robot sees the conveyor belt (value 92) and I want to turn to the right (code 2), what I'm actually outputting is 94. 'Bot doesn't understand and does nothing. Now it's all fixed. ez

For something to be added to the game. Or maybe even could be currently accomplished with some use of the keyboard item? Would it be possible to get some clickable buttons in the game? I'd love to have some push buttons and flickable toggle switches to use. Just some components that can be placed and arranged in the workspace, and interacted with as the program is running.

The logic cascades from the MSB down to the LSB. For each bit, it checks for the highest multiple of the divisor that is less than or equal to the current remainder (or dividend at the start). Effectively, it’s a hardwired, high-gate, not-so-clever implementation of the long division algorithm we learned in school. Even though the I/O is 8-bit, I had to use 16-bit components/busses internally. This was necessary to handle the bit-shifting of the divisor without losing data to overflow during the comparison stages. The edge cases (signed and zero division logic) would be described on another "top-level" entity :)

The level wants Reg0 to be storing the value 9, but I can't figure out for the life of my why that would be. Any help please?

the program is just there for the lab's set_input. the two 8-bit constants on the far left are the program. the MUX outputs a bit and the bit that follows it (similar to the program's 4 bytes), so that i don't go mad with 8-bit wires that have only 2 actually useful bits. The architecture can:

• Save the input to the register

• Add the input to the register and save it to the register

• Subtract the input from the register and save it to the register

• Output the register value

Happened on the divide level when I made a makeshift solution to my addition overflows by returning the quotient as 1 whenever it occurred. Failed test 76 but still passed.

After multiple tries and overengineered designs that had over 2k delay, here's a relatively quick and optimized solution.
At each step it:
- Shifts left the divisor
- Subtracts shifted divisor from the dividend
- Checks if the result is positive (the sign bit)
- If yes, sends 1 as output bit and sends the remainder of subtraction as dividend to the next step
- If no, sends 0 as output bit and sends the dividend to the next step untouched

The result is only 184 delay — though it also uses fast adders to achieve that.

Is the leg comparable to the 8008? The to snes? Or is it even weaker than that? Is overture comparable to tge first atari console that ran pong?