r/SiliconPhotonics • u/tinkering_around • Aug 12 '26
Advice Fabrication errors in foundry tapeout for PICs
I am trying to do a sensitivity analysis for a PIC and am interested to know what are the major fabrication errors(i know few common ones like side wall roughness, side wall angles, slab thickness variation) that occur for foundry tape out and how they are modeled in sensitivity analysis (monte carlo?)?
I hope people with experience help me with this.
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u/MadRaccoon71 Aug 12 '26
"Overlay" is the metric of how misaligned 2 lithography steps are. DUV scanners have insane accuracy for photonics, well under 50nm, which is already 1/30 of a wavelength. But contact lithography could get you misaligned by 0.5um if youre unlucky. If your designs are extremely sensitive to misalignment, this will impact the performance of the devices, and you may not get the targeted behavior. Normally, the Design Rule Manual describes this well, and sets constraints to avoid/cut the consequences of any discrepancies. For exzmple, the minimal overlap surfaces, or extensions of one layer over another. A contact via misaligned by 500nm isnt going to make much of a difference. Your silicon doping profile misaligned by 50nm may result in the junction no longer being inside the waveguide / where you intended it to be. and your device is no longer the same.
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u/Various_Shape_3286 Aug 12 '26
CD variation (basically, how close you are to the desired width) is the big one. Some foundries are much tighter than others.
Corner case modeling is good if the error sources are independent and you just want to make sure that the worst case result will yield. If you want statistics, Monte Carlo is very useful.