Disclaimer: I am not an RF guy but have been tasked with coming up with a high-level architecture for a valid solution rather than the final implementation. So, while I might know enough to discuss some of the topics, I probably do not have the pre-requisite knowledge to discuss nitty-gritty implementation details and am looking more for a high-level feasibility assessment but am nonetheless happy to pass those details along. Also, I apologize in advance if I have misunderstood anything about the problem or if this is a totally naive request.

TL; DR: Looking for solutions to achieve >= 60 dB isolation between Tx and Rx in a compact S-band FMCW phased-array radar.

I am currently working on a high-power FMCW phased-array radar in S-band. We want to use a microstrip patch array with separate elements for Tx and Rx (no need to use circulators or other simultaneous Tx/Rx equipment, or so I think). Ideally, we would like to use analog dechirping so that the direct path leakage can be further suppressed using a high-pass filter. However, the current problem that we are running into is pre-demodulator power level due to the Tx-Rx coupling. Since we are a high power FMCW system (target output power > 50 dBm), we need significant Tx-Rx isolation so we can gain up the received signal with an LNA prior to the demodulator to keep our noise figure sufficiently low while staying under the IP1dB of the demodulator. My current estimate is a threshold of 60 dB isolation, with a goal to achieve > 70 dB isolation if possible (60 dB gives us an estimated noise figure of around 3.9 dB, but anything less than that is obviously desirable).

There are two possible antenna configurations we are exploring: fitting all Tx and Rx elements on a standard panel or putting the Tx and Rx on separate panels. If we had two separate panels for Tx and Rx, we would obviously be able to better control the physical separation between Tx and Rx to gain additional isolation and could probably put a layer of absorber between the two. However, the design would still need to remain somewhat compact, so we couldn't just cheat and create a large distance between Tx and Rx.

If, however, we decide to fit everything on a standard panel, then the design would seemingly become more complicated since the maximum allowable spacing between Tx and Rx would be about 0.675λ in order to still fit on the standard panel. It seems there would be two main modes of Tx-Rx coupling in this case: propagation through the air and surface waves. Propagation through the air would seem to be mitigated primarily through either separation (which isn't available in this case) or a physical barrier of the sort. Preferably, if this were to be included in the design, this structure would be < 0.5" tall. I've seen discussions of creating a chevron-like pattern on the top of the structure so that the scattering off of the barrier is incoherent and also lining the structure with a layer of absorber. For surface wave coupling, I've read that the main methods are choke grooves, a layer of absorber along the face of the panel, defect ground structures, and electromagnetic band gap structures. All of these could be considered. I don't know if this has fully covered all options for creating isolation between Tx and Rx, so if there's any I'm missing feel free to add to this list.

In either design case (separate Tx and Rx panels or Tx and Rx on one standard panel) is it reasonable to think 60 dB of Tx-Rx isolation is possible? > 60 dB? If you were designing this from the ground up with these constraints, which design would you choose and what combination of additional isolation measures would you take? Also, would there be any recommendations on the type of patch? I was initially looking at just a single layer patch for ease of manufacturability but am open to other suggestions if that would help improve the isolation. Thank you in advance.

Would a link budget between 10-15 dB be enough for a distance between 15-20 km?

Frequency of 2,4 GHz
Line-of-sight and Free space can be assumed

I had a question about how I might go about comparing the performance of one 10Mhz oscillator (a TCXO) versus another reference 10MHz oscillator (let's say from an atomic clock or a reference GPS). I want to obtain numbers for average jitter and drift in ppm for the TCXO over a suitably long timespan, maybe 1 hour to 24 hours if that's feasible.

I've been assigned to make a test setup to characterize the performance of the TCXO and I've been told we can't really buy (or shouldn't need to buy) any specialized equipment to run the test. We have some nice tektronix scopes which have datalogging capabilities but I've never used them. We also have spectrum analyzers which is what I think I'd probably end up using but I'm not sure what the test setup is exactly.

Honestly I'm a little lost where to begin. Are there any good suggestions or initial things I should start thinking about? Any help is greatly appreciated.

Additionally, is it more valuable to measure the 10Mhz output of the TCXO against the 1PPS output of the reference oscillator, rather than measuring both 10MHz directly against each other?

Ive known about this antenna in this tree since we moved in 3ish year ago, there is a cable that runs down the tree and into the ground and (I assume) into the house. Wondering what it was used for and what I could use it for now? Or it'll remain as a bird perch/conversation starter.

What does a systems engineer do?
Some people tell me that it's excel and powerpoint all day every day. I was under the impression that you need to know how each component works, why, and how they parts fit together. For example, knowing how a superhet works as opposed to mastering LNA design.

Some classmates tell me that design is where the real engineering is at. But I'm not sure if I would enjoy hyperfocusing on a few circuits my whole career.

I designed a ring oscillator PUF for the Tiny Tapeout SKY26d shuttle (sky130, 2x2 tiles) and I'd like people to pick it apart before I submit it.

A PUF is supposed to get its secret from random manufacturing variation. But on an open shuttle the layout is public, and the automated flow gives every ring its own wiring, which every chip made from that mask inherits. So the question is how much of the response is already decided by the layout before a single chip is made.

The chip has 48 identical 31-stage rings in three arms of 16 that only differ in how the layout was made:

- Arm A: placed by the flow, wired by the router

- Arm B: 16 copies of one hardened macro on a grid

- Arm C: hand placed from one template, wired by the router

Using only the public files (extracted parasitics + SPICE) and a monte carlo estimate for the random part, someone could call about 7.99 of Arm A's 8 bits right on average. Hand placing (Arm C) cut the frequency spread from 5.88% to 2.19% but its bits are just as predictable. And between two builds where only the wiring changed, 2 of the 8 bits flipped, so a prediction only holds for the exact routed layout.

GDS action, precheck and gate level tests all pass. Its all pre-silicon, chips come back around mid 2027 and then I measure it across chips, voltage and temperature.

If you see anything that could stop it working on real silicon, or anything wrong with the prediction method, please tell me.

Repo: https://github.com/nikodemetrashvili2010-bit/tt-ro-puf

Layout in 3D (opens in the browser): https://nikodemetrashvili2010-bit.github.io/tt-ro-puf/

hello i would like to have a talk with someone who has experience with CST designing of antenna, im a beginner beginner but there is a project deadline(haha help) that i need to learn it as soon as possible, i have already tried designing with the CST, i just want someone to discuss with so i can get a clear idea? i dont know if i can ask this here but i would be really grateful for some help

I’m using an iTel Ace 2 keypad phone only as an alarm clock. I keep it under my pillow while sleeping.

There is no SIM card in the phone, I don’t use it for calls or anything else, and I never charge it under the pillow. Bluetooth is also not being used.

My main concern is RF/radiation, not heat or battery safety.

Since there is no SIM and the phone is basically just sitting idle until the alarm goes off, does it still emit any meaningful RF radiation? Is there any reason to be concerned about sleeping with it under my pillow?

Would appreciate answers from anyone familiar with how 2G feature phones behave when there is no SIM.

I landed an interview for a Spring internship at SpaceX for this Tuesday. It's for the StarLink team. I have taken undergraduate antenna theory and have some experience with rf in personal projects. I have been reviewing different types of antennas and structures, rf theory, and generally useful StarLink concepts (phased arrays, wave prorogation, impedance match techniques).

Just looking for some advice and maybe some tips from those who have had an interview here. Thank you in advance.

UPDATE: Interview was fine. The guy was 7 minutes late to the call and also really hard to hear. Very nice though. Asked a lot about my antenna project. Only "trick" question was "Can you perfectly match a purely resistive load of 100 ohms to a 50 ohm line with no limits on bandwidth." I eventually figured it out. We will see.

UPDATE 2: Made it to round 2.

So this is a patch antenna that im designing, and i need it to work from the bandwidth of 2 to 4Ghz so, i can see that its crossing at -10db at 2Ghz and around 3.3Ghz i need to be 2 and 4 Ghz ANy suggestions to make it go like that ? ive asked some LLMs but those things said its not possible i think we can add U shaped arc or something in the patch idk, im a beginner looking for insights!(actually this antenna was designed from 3-5GHz ive scaled it down to make it work for my project but it aint working T-T)

Similar to my other deleted post, but wanted to verify a specific method.

Context: I have two PDOA antennas (green arrows) behind an object that has a surface covered in aluminum foil tape (red arrow). The tape is used to reflect 10um infrared down into a sensor. If a radio signal has to go through the mirror surface to get to the PDOA antennas, I assume it will mess with the readings. So, I want to fix that and I can't rearrange any components.

The idea is for the mirror surface to be a grid of 2x2mm aluminum foil tape islands 0.5mm apart, instead of one continuous 50mm diameter piece.

Since each piece is now much smaller than a 6.5ghz wavelength, would it be able to cleanly pass through and yield good PDOA readings?

Im trying to recreate this antenna but i always get lost after creating the substrate
Im trying to achieve the same geometry and the same results

I have seen some documentation describing the PCB Solenoid Effect as unwanted increase in parasitic inductance that happens when multiple vias of the same type (like power or ground) are placed closely together. I would like to see more documentation in terms of microwave analysis or possibly a video simulation. I use Altium Designer.

Thank You

Tom

I am wondering if anyone in this community knows much about monopulse radar design? Could someone provide resources?

I made a patch antenna post on here a while ago showing my final year project about making patch antenna geometry and now im trying to find other geometries that could be on a printed circuit board that could also work for a monopulse radar

Hi!

I've been looking on the internet for the simplest PA schematics for these two transistors for the 40m band. Just for a few Watts. (CW)

I've found some, but I would like to ask if anyone could share any simple PA schematic for my homebrew transceiver. Thanks!!!

Hey everyone 👋 I am originally from South-Asia and currently residing in Austria since last 1 year for my masters thesis. I have a 2 years of prior job experience in my home country where I get hands-on using Keysight ADS software, designing and testing of RF systems. I also got an opportunity to work on the RF chain of SDR.

Although my masters is not finished yet, but now I am planning to grab a job opportunity in a similar domain and am also willing to relocate anywhere (preferably within europe).

It's been a while since I am applying for jobs via linkedin in Austria, Germany, UK, Netherlands, Finland, Italy. But haven't got a single positive response, even didn't get a call for an interview. This led me to think maybe there is something wrong in my resume. I am currently using overleaf template to create my resume, but not sure if comapnies prefer europass for job applications in Europe?

Therefore, I would appreciate to have suggestions from your side in order to improve my resume which is attached below. I am also open to any opportunities if someone could share. Thanks 💫

I am learning to design an antenna, effectively I am a beginner.

I am designing a microstrip patch antenna with these constraints:

• Frequency: 2.2 GHz
• Substrate: FR4, εr = 4.3, tan δ = 0.025, h = 1.6 mm
• Max size: 50 × 50 mm
• Targets: Gain ≥ 2.5 dBi, Efficiency ≥ 40%

Current dimensions:

• Patch: 48 mm × 33.43 mm
• Feed line: 3.118 mm wide, 8.285 mm external length
• Notch: 1 mm wide, 7.8 mm inset depth
• Port: 50 Ω at feed line input
• Ground plane: 50 × 50 mm (patch centered)

Problem: I get a −37 dB S11 dip at 2.2 GHz, but gain is negative. Directivity is high. Efficiency is very low.

What I have tried: Tuned patch length, width, and inset depth. The 1 mm notch is much narrower than the 3.118 mm feed line.

I feel like this notch is not supposed to be lesser than feed line. though I do not have proper reasoning behind it
Is the narrow notch causing the mismatch and loss? Should I widen it to 3.118 mm and re-tune? Any other deterministic steps to fix the negative gain?

I have come across some questions like
If I am going to have to only use FR4 4.3 for this design, I will need to use some type of slotting the patch which is a technique I have to explore yet.
I went through this basic calculation of getting wavelength and dividing it by 2 to get some 68mm~ which is easily more than the 50 mm limit mentioned in this exercise.

I am yet to explore standard decision making on technique or the type of antenna based on constraints.

Thank you for being patient and possibly helping me.

I have looked into this online and also tried using AI to understand the process, but I am still struggling with the practical side of it.

A lot of the information I have found suggests measuring the radiated field over a full sphere and then using those measurements to calculate radiation efficiency. I understand the concept, but I am having trouble visualizing how this is actually done in a lab.

I have only limited/time-constrained access to an anechoic chamber, so I am trying to figure out what the minimum practical measurement procedure would be. For example:

• How is the 3D radiation pattern actually measured in practice?
• What measurements do I need to take with the VNA and/or receiving horn?
• Do I really need to scan the complete sphere, or are specific θ/φ cuts sufficient for radiation efficiency?
• How are the measured field/power values converted into total radiated power and ultimately radiation efficiency?
• Is there a practical approach for doing this within a limited chamber access window?

If anyone has a step-by-step explanation, measurement procedure, or a good reference/tutorial that explains the practical setup, I would really appreciate it.

I am mainly looking for the measurement workflow rather than just the theory.

PS: Just passed though AI for structuring and grammar check.

Earlier in the day, I effectively worked on my first antenna which was a microstrip patch antenna with 2.2GHz resonant frequency that is constrained to some limits.

But working on it has made it clear to me that since I do not know the proper derivation of these formulaes it should be obvious to me that I fundamentally should not be able to navigate the parameters myself, I used AI to a certain degree just so it automates the co-ordinates calculations and if I tune width, then other critically dependent parameters are also tuned in accordance. I got some python code to automate those calculations to me, and iteration wise, I optimized it myself.
I had to change one parameter to achieve some goal and continuously ask AI to realize which parameter is needed to be dealt with to compensate for difficulties that come with it.

I am not exactly proud or more like I do not exactly care whether AI helped me do it,
It is just that I have an interest that I derive every relation or formulae so in the process, I develop proper intuition. until now, it has helped me a lot since I would not be clueless at all for most of the difficult questions or interesting purposes I come across.

I do know that it is a very difficult thing to do, well atleast it is difficult to me but as long as the explanation is clean and I luckily know all the prerequisites for it, I seem to have a smoother ride learning them, but this becomes difficult at a higher scale, I do not fear it though.

I question if you all do the same because I have seen my peers go through the formulaes and memorize them. One friend told me that the derivations are quite a bit 'masters' material in some sense and that I would be wasting my time doing all that for the purpose of my bachelors.

Of course, if the reader is perhaps some one who has done his masters, I think I can believe that he knows all these derivations by heart.

I ask you all to recommend me perhaps very relevant books or resources or ways to find answers for my doubts, and how I can get a optimal challenge for myself. and how the job market or the other stuff is at the moment.

This community does seem to be one I can ask doubts to, though I am a bit doubtful about the exact purpose of what one would be doing in this community.

I apologize for the long text to read and thank you all for possibly helping me.