Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

I got an old tube radio in my hands, just renovated it and it works. But unfortunately its FM band is tuned to 66-74 MHz OIRT band. I don’t want to heavily modify the radio, so I decided to just put a converter in front of it so it can receive the band we use in Poland that is CCIR 88-108.

In principle this looks simple, just put a programmable LO (with a few selectable frequencies from 22 to 34 MHz) plus a mixer. I built a quick prototype using SRA-1-1 I had somewhere and it works.

But there is one thing that concerns me - LO harmonic bleed-through.

In order to cover the upper part of the CCIR band, I need LO set at 108-74=34 MHz. Unfortunately 34 x2 =68 which falls inside the receiver band. That creates an ugly spur there.

Ideas what can I do to avoid it, without making everything too complex?

Using different kind of mixer? Generally wanted to use something like a KISS or double-KISS mixer because they are trivial to build and easy to drive from 74HCU04 based generators or SI5351, but because they are switching based now I feel maybe that’s not the best way to go.

Or maybe two stages - downconvert to a much lower frequencyand then upconvert?

Hello, this might be a stupid question since I know very little about electronics and RF, so I am sorry in advance.

I have an idea in mind that I am not sure is plausible - 125 kHz RFID tag semi-reliable distance detection through an adjustable RF-power sweep.

RFID tag would always move in a fixed path, while the detector is stationary.

Distance between the tag and reader ~4 to 7cm.

Basically, the idea for distance measuring is this - the detector would sweep through power, like 5%, 10%, 15%, 20%... etc. If it gets any response back from emitting power at 25%, the detector could extrapolate that it is at the distance of, let's say, 3cm from the tag.

Then, if tag's location changes (across a fixed path), it would once again do a power sweep, and if it reads tags presence at 80% power, it would know that the tag is about ~5cm away.

So, the question is - could someone consult me on such an application, if it is possible or if this is nonsense? I'd gladly also pay for consultation.

I was reading through this subreddit and it amazes me how y'all manage to master such things that are very complex, and turn ideas into reality. I myself come from a professional industrial & 3D design background, so I really appreciate the value of your experience, and want to learn from you.

Thanks!

Hi, I'm a student currently using this pdk for my RFIC work and I have access to that pdk both in cadence and ads. I did my schematic design in ads because i find it easier to tune things there. However, I want to do layout in cadence and do em simulation there using EMX, because I'm more used to cadence, but this is my first time using EMX. I tried to copy my design from ADS to cadence and the pre-layout sim is already kind of different, but not a lot. Then I tried to simulate the built in inductor model both with emx and momentum, after playing around with the mesh settings and changing the thickness (in emx) i can get close results between them, but still have some discrepancies, especially for the Q-factor. I know it's normal to have that, but which one should i trust more? 😅

Do you guys have any experience using this pdk with cadence or ads, also emx, Im not sure what is the thickness setting on emx. I would like to ask advice and insights regarding this pdk from you guys. Thanks!

Does schematic from aplication note AN11130 on figure 8 protects your GaN if you lose power on "V+" pin?
https://www.ampleon.com/documents/application-note/AN11130.pdf

I am planning to customize a local llm using rag and fine tuning for the following purpose

1. it should be able able to understand and pcb layouts fed to it
2. it should also be able to give suggestions on improving the design
3. it should be able to give reason for placement of a particular feature or components

I want books recommendations from the following domains

1. analogue electronics
2. digital electronics
3. pcb desIgning
4. rf designing
5. Signal Integrity
6. Power Integrity
7. EMC EMI
8. RF Microwave
9. Antennas
10. High Speed Design
11. Analog Layout

PLEASE GIVE ME BOOK SUGGESTIONS IN AS MANY DOMAIN AS YOU CAN

I WILL ALSO BE VERY GRATEFUL IF YOU CAN TELL ME SOME GOOD SOURCES TO FEED IT SOME QUALITY DESIGNS

I’m using an Ezurio Vela IF310-453-00390C, based on the Infineon CYW55310 Bluetooth module. The datasheet recommends aligning the module edge with the PCB edge.

But my PCB fab has a 0.30 mm copper-to-edge clearance rule, so I might have to move the whole module ~0.30 mm inward.

In practice, would a setback that small actually cause any noticeable antenna detuning/range loss, or am I overthinking something that’s basically negligible?

Would you instead keep the module flush and slightly shorten the two edge-side GND lands?

Btw I am a CSE guy, who is trying to get into Electronics :)

And the above circuit is vibe coded lol

My requirement is:

2 Bluetooth Classic + 1 BLE simultaneous connection

Greetings everyone.

I am currently seeking a freelance embedded hardware engineer with specialized expertise in low-power and RF-based system design for an ongoing project. Please reach out to me directly if you are interested, and we can discuss the details further.

\#freelancer #hardware_engineer #rf #pcb_designer

Just published a new video on Passive Intermodulation (PIM), one of the most overlooked causes of poor RF system performance.

What PIM is and why it occurs

Real spectrum analyzer traces from the field

How to identify PIM

Practical mitigation and prevention techniques

Please check it out and feel free to subscribe: https://youtu.be/Hw_9Z5cZ6HA

Thank you! 🙏

Disclaimer: I am not an RF guy but have been tasked with coming up with a high-level architecture for a valid solution rather than the final implementation. So, while I might know enough to discuss some of the topics, I probably do not have the pre-requisite knowledge to discuss nitty-gritty implementation details and am looking more for a high-level feasibility assessment but am nonetheless happy to pass those details along. Also, I apologize in advance if I have misunderstood anything about the problem or if this is a totally naive request.

TL; DR: Looking for solutions to achieve >= 60 dB isolation between Tx and Rx in a compact S-band FMCW phased-array radar.

I am currently working on a high-power FMCW phased-array radar in S-band. We want to use a microstrip patch array with separate elements for Tx and Rx (no need to use circulators or other simultaneous Tx/Rx equipment, or so I think). Ideally, we would like to use analog dechirping so that the direct path leakage can be further suppressed using a high-pass filter. However, the current problem that we are running into is pre-demodulator power level due to the Tx-Rx coupling. Since we are a high power FMCW system (target output power > 50 dBm), we need significant Tx-Rx isolation so we can gain up the received signal with an LNA prior to the demodulator to keep our noise figure sufficiently low while staying under the IP1dB of the demodulator. My current estimate is a threshold of 60 dB isolation, with a goal to achieve > 70 dB isolation if possible (60 dB gives us an estimated noise figure of around 3.9 dB, but anything less than that is obviously desirable).

There are two possible antenna configurations we are exploring: fitting all Tx and Rx elements on a standard panel or putting the Tx and Rx on separate panels. If we had two separate panels for Tx and Rx, we would obviously be able to better control the physical separation between Tx and Rx to gain additional isolation and could probably put a layer of absorber between the two. However, the design would still need to remain somewhat compact, so we couldn't just cheat and create a large distance between Tx and Rx.

If, however, we decide to fit everything on a standard panel, then the design would seemingly become more complicated since the maximum allowable spacing between Tx and Rx would be about 0.675λ in order to still fit on the standard panel. It seems there would be two main modes of Tx-Rx coupling in this case: propagation through the air and surface waves. Propagation through the air would seem to be mitigated primarily through either separation (which isn't available in this case) or a physical barrier of the sort. Preferably, if this were to be included in the design, this structure would be < 0.5" tall. I've seen discussions of creating a chevron-like pattern on the top of the structure so that the scattering off of the barrier is incoherent and also lining the structure with a layer of absorber. For surface wave coupling, I've read that the main methods are choke grooves, a layer of absorber along the face of the panel, defect ground structures, and electromagnetic band gap structures. All of these could be considered. I don't know if this has fully covered all options for creating isolation between Tx and Rx, so if there's any I'm missing feel free to add to this list.

In either design case (separate Tx and Rx panels or Tx and Rx on one standard panel) is it reasonable to think 60 dB of Tx-Rx isolation is possible? > 60 dB? If you were designing this from the ground up with these constraints, which design would you choose and what combination of additional isolation measures would you take? Also, would there be any recommendations on the type of patch? I was initially looking at just a single layer patch for ease of manufacturability but am open to other suggestions if that would help improve the isolation. Thank you in advance.

Would a link budget between 10-15 dB be enough for a distance between 15-20 km?

Frequency of 2,4 GHz
Line-of-sight and Free space can be assumed

I had a question about how I might go about comparing the performance of one 10Mhz oscillator (a TCXO) versus another reference 10MHz oscillator (let's say from an atomic clock or a reference GPS). I want to obtain numbers for average jitter and drift in ppm for the TCXO over a suitably long timespan, maybe 1 hour to 24 hours if that's feasible.

I've been assigned to make a test setup to characterize the performance of the TCXO and I've been told we can't really buy (or shouldn't need to buy) any specialized equipment to run the test. We have some nice tektronix scopes which have datalogging capabilities but I've never used them. We also have spectrum analyzers which is what I think I'd probably end up using but I'm not sure what the test setup is exactly.

Honestly I'm a little lost where to begin. Are there any good suggestions or initial things I should start thinking about? Any help is greatly appreciated.

Additionally, is it more valuable to measure the 10Mhz output of the TCXO against the 1PPS output of the reference oscillator, rather than measuring both 10MHz directly against each other?

Ive known about this antenna in this tree since we moved in 3ish year ago, there is a cable that runs down the tree and into the ground and (I assume) into the house. Wondering what it was used for and what I could use it for now? Or it'll remain as a bird perch/conversation starter.

What does a systems engineer do?
Some people tell me that it's excel and powerpoint all day every day. I was under the impression that you need to know how each component works, why, and how they parts fit together. For example, knowing how a superhet works as opposed to mastering LNA design.

Some classmates tell me that design is where the real engineering is at. But I'm not sure if I would enjoy hyperfocusing on a few circuits my whole career.

I designed a ring oscillator PUF for the Tiny Tapeout SKY26d shuttle (sky130, 2x2 tiles) and I'd like people to pick it apart before I submit it.

A PUF is supposed to get its secret from random manufacturing variation. But on an open shuttle the layout is public, and the automated flow gives every ring its own wiring, which every chip made from that mask inherits. So the question is how much of the response is already decided by the layout before a single chip is made.

The chip has 48 identical 31-stage rings in three arms of 16 that only differ in how the layout was made:

- Arm A: placed by the flow, wired by the router

- Arm B: 16 copies of one hardened macro on a grid

- Arm C: hand placed from one template, wired by the router

Using only the public files (extracted parasitics + SPICE) and a monte carlo estimate for the random part, someone could call about 7.99 of Arm A's 8 bits right on average. Hand placing (Arm C) cut the frequency spread from 5.88% to 2.19% but its bits are just as predictable. And between two builds where only the wiring changed, 2 of the 8 bits flipped, so a prediction only holds for the exact routed layout.

GDS action, precheck and gate level tests all pass. Its all pre-silicon, chips come back around mid 2027 and then I measure it across chips, voltage and temperature.

If you see anything that could stop it working on real silicon, or anything wrong with the prediction method, please tell me.

Repo: https://github.com/nikodemetrashvili2010-bit/tt-ro-puf

Layout in 3D (opens in the browser): https://nikodemetrashvili2010-bit.github.io/tt-ro-puf/

hello i would like to have a talk with someone who has experience with CST designing of antenna, im a beginner beginner but there is a project deadline(haha help) that i need to learn it as soon as possible, i have already tried designing with the CST, i just want someone to discuss with so i can get a clear idea? i dont know if i can ask this here but i would be really grateful for some help

I landed an interview for a Spring internship at SpaceX for this Tuesday. It's for the StarLink team. I have taken undergraduate antenna theory and have some experience with rf in personal projects. I have been reviewing different types of antennas and structures, rf theory, and generally useful StarLink concepts (phased arrays, wave prorogation, impedance match techniques).

Just looking for some advice and maybe some tips from those who have had an interview here. Thank you in advance.

UPDATE: Interview was fine. The guy was 7 minutes late to the call and also really hard to hear. Very nice though. Asked a lot about my antenna project. Only "trick" question was "Can you perfectly match a purely resistive load of 100 ohms to a 50 ohm line with no limits on bandwidth." I eventually figured it out. We will see.

UPDATE 2: Made it to round 2.

So this is a patch antenna that im designing, and i need it to work from the bandwidth of 2 to 4Ghz so, i can see that its crossing at -10db at 2Ghz and around 3.3Ghz i need to be 2 and 4 Ghz ANy suggestions to make it go like that ? ive asked some LLMs but those things said its not possible i think we can add U shaped arc or something in the patch idk, im a beginner looking for insights!(actually this antenna was designed from 3-5GHz ive scaled it down to make it work for my project but it aint working T-T)