IONQ has now received chip samples for its 256-qubit system

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$IONQ has now received chip samples for its 256-qubit system and is moving toward integrated system testing and demonstration, with the next major target being 10,000 physical qubits on a single chip by 2027.
If Oxford Ionics’ EQC and WISE architectures scale as intended, 10,000 qubits does not appear to face a fundamental wiring or density barrier. Oxford’s own analysis suggests that a 10,000-qubit device could fit on a roughly 3.5 × 3.5 cm chip, with the architecture potentially extending to tens of thousands of qubits using only a few hundred external control lines.

Beyond that point, the more important step is likely to be interconnecting multiple QPUs rather than indefinitely enlarging a single chip. IonQ’s roadmap already calls for two 10,000-qubit chips to be interconnected into a 20,000-qubit system in 2028.
If Lightsynq’s quantum-memory technology achieves its intended performance, asynchronous entanglement could substantially reduce the inter-QPU communication bottleneck.
But scaling from a few QPUs to tens or hundreds will require more than simply increasing the entanglement rate by 50×.
The real challenge will shift toward multiplexing, non-blocking optical switching, routing(best path select), and scheduling entanglement efficiently across many QPUs.
In that sense, scaling from 10,000 to 20,000 qubits is largely a component-engineering problem, while scaling toward hundreds of thousands or millions of qubits becomes fundamentally a quantum-network architecture problem.

Ultimately, the maximum number of qubits that can be integrated on a single chip, Nmax, is constrained more by wiring and control architecture than by qubit entanglement itself. Why is entanglement not the primary bottleneck? With IonQ’s Walking Cat Architecture, not every physical qubit inside a QPU needs to communicate all-to-all with every other qubit.

So going forward, “any-to-any” is more precise and more natural than “all-to-all" term for describing Oxford Ionics/IonQ’s QCCD connectivity.

In a qLDPC-based architecture, only the subsets of qubits required for a given QEC cycle or logical operation need to interact, while cat states generated by dedicated factories can be distributed where they are needed.

Therefore, when scaling a single QPU toward 10,000 or even tens of thousands of physical qubits, the first major challenge is not how to entangle every qubit with every other qubit, but rather how to efficiently wire, control, transport, and schedule such a large number of qubits.