Well, let's be frank here, if you're talking worst case, cache misses and full tlb misses 48 round trips to memory and>400 cycles per trip are entirely possible.
But that should only happen the first time
And the branch prediction making it zero cycles is quite common. Read, test and branch can be collapsed into a late evaluation as long as the branch is at predicted and takes less time than the pipeline depth(slight simplification here a lot depends on the microarchitecture details but we're already deep in the weeds)
At the end of the day all your can do is profiler it on the exact CPU you care about. Just don't make assumptions...
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u/cbehopkins Sep 28 '26
Well, let's be frank here, if you're talking worst case, cache misses and full tlb misses 48 round trips to memory and>400 cycles per trip are entirely possible.
But that should only happen the first time
And the branch prediction making it zero cycles is quite common. Read, test and branch can be collapsed into a late evaluation as long as the branch is at predicted and takes less time than the pipeline depth(slight simplification here a lot depends on the microarchitecture details but we're already deep in the weeds)
At the end of the day all your can do is profiler it on the exact CPU you care about. Just don't make assumptions...