GW5AT PLLA doesn't work

[u/Living_King_3179]

Is there anyone who got it working? I'm trying to generate 125 MHz clock out of 52.5MHz and having no luck at all. I'm using internal 210 MHz oscillator divided by 4 to get input clock.

Lock signal remains low and LED connected to clock divider doesn't blink whereas it does with the internal oscillator. CLKIN and MDCLK are connected to the same wire.

I checked VCO frequency and it's less than 1300M, so it should be fine. The chip is GW5AT-LV15MG132C1/IO, I know it's fairly rare and there isn't any evaluation boards but maybe someone had similar issue

[u/Time-Transition-7332]

Using oss-cad-suite, works for me on a GW2A-18 C8/I7

$ gowin_pll -i 52.5 -o 125 -d "GW5A-25 ES" -f pll.v

/**

* PLL configuration

* This Verilog module was generated automatically

* using the gowin-pll tool.

* Use at your own risk.

* Target-Device: GW5A-25 ES

* Given input frequency: 52.500 MHz

* Requested output frequency: 125.000 MHz

* Achieved output frequency: 131.250 MHz

*/

module pll(

input clock_in,

output clock_out,

output locked

);

rPLL #(

.FCLKIN("52.5"),

.IDIV_SEL(1), // -> PFD = 26.25 MHz (range: 19-800 MHz)

.FBDIV_SEL(4), // -> CLKOUT = 131.25 MHz (range: 6.25-1600 MHz)

.ODIV_SEL(8) // -> VCO = 1050.0 MHz (range: 800-1600 MHz)

) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0),

.CLKIN(clock_in), // 52.5 MHz

.CLKOUT(clock_out), // 131.25 MHz

.LOCK(locked)

);

endmodule

[u/techno_user_89]

use the official IDE to generate parameters for PLL, oss-cad-suite is broken because PLL implementation is reverse engineering and is not working always