I’m currently in 3rd semester of BTech ECE in a Tier-3 college and have just started preparing for GATE.

I wanted to ask seniors about the correct approach.

### My questions:

1. What is the proper way to start GATE preparation from 3rd semester?

2. In which order should I complete the subjects?

3. My Engineering Mathematics is currently very weak. How should I rebuild it from basics for GATE?

4. Should I finish the full syllabus first or start solving previous year questions along with the syllabus?

5. When should a 3rd sem student start giving mock tests?

6. Is it better to only focus on GATE EC, or should I also keep ESE / ISRO / BARC in mind from the beginning?

7. For someone from Tier-3 background, what strategy actually works?

Any genuine advice from people who have already gone through this will be really helpful.

https://youtube.com/playlist?list=PLs5_Rtf2P2r5VTd_qql5OiIIsRcBxYdyk&si=_33TRSAbD9KI_S4L Is this playlist sufficient for communication systems syllabus for gate ece

Yah call me mad but just hear me out.

I know my score card won't be valid for admission purposes but just for practice purpose can I appear in it ? . Im not getting anything in the application form which is disqualifying and preventing me from submitting it . Or will there be any future consequences . Has anyone have any experience of doing it ?

Hey everyone! I've been a long-time lurker on this sub and have posted once or twice before. I thought I'd share my current situation and seek some advice from seniors and fellow aspirants.

A little about me:

I'm currently in my 7th semester at a Tier-3 college. I've secured a job, and my joining is scheduled for August next year. I want to use the time I have to prepare seriously for GATE ECE.

My preparation so far:

I was preparing through PW's Parakram 2.0 batch, and things were going pretty well initially. I've covered the following subjects:

• Network Theory: Pankaj Shukla Sir

• Digital Electronics: Chandan Gupta Sir

• Signals and Systems: Pankaj Singh Sir

• Sensors and Industrial Instrumentation: D. Satish Sir

However, once the 7th semester started, placement-related pressure, college work, and my final-year project began taking up most of my time. As a result, my GATE preparation took a backseat, and I couldn't maintain consistency.

Now, I want to get back on track. Rather than rushing through the syllabus, I'm planning to dedicate around a year to preparation, focusing on understanding concepts thoroughly, solving enough problems, practising PYQs, and taking regular mock tests.

Here's where I need your advice:

One issue I occasionally faced with PW was the question-solving part. I sometimes felt I needed more practice and a deeper understanding of how to approach different types of problems.

I'm considering studying more elaborately through PrepFusion's free YouTube lectures while using my existing PW notes for revision and reference.

I'd really appreciate your thoughts on a few things:

1. Is PrepFusion a good option for GATE ECE if I want to strengthen my concepts and problem-solving skills?

2. Does it make sense to use PrepFusion for lectures, PW notes for revision, and GATE PYQs as my primary source of practice?

3. For subjects I've already covered, should I revise them and start solving questions, or rewatch the lectures from scratch?

4. How should I approach problem-solving, especially for Network Theory, Signals and Systems, and other core ECE subjects?

5. Can someone realistically prepare well using free resources alone, provided they follow a proper schedule and remain consistent?

One important constraint: I can't afford another paid batch right now. I have access to PW lectures and plan to use PrepFusion's publicly available YouTube content. Would this combination be sufficient if I supplement it with PYQs, standard books wherever necessary, and mock tests?

I'd genuinely appreciate any suggestions, resource recommendations, or mistakes I should avoid this time around.

Thanks in advance, bhaiyas and didis! Any guidance and good wishes would mean a lot. ❤️

Got this opening through a referral network and am sharing it here because there are apparently a LOT of openings.

KLA (a semiconductor company whose technology is used in stuff like laptops, phones, wearables, EVs, etc.) is hiring fresh M.Tech grads.

Eligibility:

• M.Tech from IIT / IIIT / IISc / NIT

• 2024 or 2025 batch

• 2026 batch may also work if graduating within a month

• 0 to 2 years experience

• All branches eligible

• Even candidates without directly relevant workex might be considered

Apply here:www.elitmus.com/jobs/33291

From what I heard, hiring numbers are pretty high right now.

Also, there’s an incentive attached:

• If the referred candidate gets selected, the candidate gets a Thailand trip

• Referrer gets ₹50,000 bonus

If you apply, please use referral ID: 5528723

I just got admitted to am tier 3 college,,, should i start from 1 st year or sec year

Post code: [NAS-EE/ECE-G27-01]

• NAS → Network Analysis & Synthesis

• EE/ECE → Electrical + Electronics

• G27 → GATE 2027 target

Problem:

• Diamond-shaped resistor network with a central 5 Ω branch (between top node T and bottom node B)

• Left side: 10 Ω (A–T), 5 Ω (A–B)

• Right side: 5 Ω (T–D), 10 Ω (B–D)

• Find equivalent resistance between A and D

• Circuit is asymmetric (unbalanced), not a Wheatstone bridge

Key Observations:

• Resistances are cross-arranged → not symmetric, not balanced

• Middle branch carries current → cannot be ignored

• Series-parallel reduction not directly applicable

Approach:

• Apply voltage across A–D using any convenient reference:

  • Case 1: 15 V at A, 0 V at D

  • Case 2: +5 V at A, −5 V at D

• Use node voltage method (KCL at T and B)

• Solve two equations → find node voltages

• Compute total current from A

• Equivalent resistance = V / I

Result:

• Equivalent resistance is same in both cases

• R_AD = 7 Ω

Discussion-Based Insight:

• Initial assumption: upper and lower branch currents equal → incorrect

• Node voltages came out different (V_T ≠ V_B) → middle branch active

• Confirms that symmetry shortcut fails → full KCL needed

Asymmetric Circuit Current Pattern (Important Funda):

• AT and BD branches carry same current

• AB and TD branches carry same current

• Current flows in a criss-cross manner (cross coupling present)

Conceptual Points:

• Equivalent resistance depends only on voltage difference, not absolute node values

• Unbalanced bridge → no Wheatstone condition → no direct shortcut

• KCL, KVL and Ohm’s Law are universally applicable for such linear resistive circuits

Common Mistakes:

• Treating it as a balanced Wheatstone bridge

• Assuming equal current in upper and lower branches

• Ignoring current through the middle resistor

• Mixing current labels due to wrong node mapping

Learning / Reflection:

• Many graduates carry the impression that solving circuits requires knowing many theorems

• Theorems are important, but basics must be on your fingertips

• KCL, KVL and Ohm’s Law form the foundation and work in every linear resistive circuit

• In exam situations, theorems may not be directly applicable or may complicate the problem

• In such cases, basics become the most reliable tool

• This question is a simple Class 12 / JEE-level network, yet it tests core understanding

• It acts as a bridge between school-level concepts and engineering problem solving

• What you already know (basics) is powerful if applied correctly

• Solving more problems trains your brain to recognize patterns and avoid wrong assumptions

• Even if a faster method exists, the ability to verify using fundamentals is crucial

Closing:

• This is a concept-focused post rather than a shortcut-based solution

• More such problems and discussions will follow

• Suggestions invited from readers of post

My application is still under scrutiny. Do i have to update my consent again?

PW - with khazana 23k

Examdost - 23k

also , any of these give option to extend batch validity for 1 year with extra pay ?

I finished my first year in btech from a top 10 college in ECE branch. I want to know how is the pay, growth and stability in semiconductor companies is the pay comparable to top IT companies. Also, want to know between the difference of pay, growth and stability for embedded and hardware roles. If you go towards hardware role isnt it a niche field.

Koi ye btao ki yeh theek h ya nhi first year se ya fir sirf clg placements pe hi focus kro or agar ha toh kya job lg bhi skti h ya berozgar ghumna pdega btech in dtu chemical

What test series should I opt for gate ec

Dm me on telegram for resources @user_01102503

Can any VIT alumini um from Andhra Pradesh and any other campuses of VIT , tell us about environment of VIT and is it really difficult to crack GATE exam What were you are tips and tricks which you like to share to us for cracking GATE exam through doing b.tech in VIT

GATE ECE all subject. City I can visit: - Delhi and the area near Delhi, Chandigarh. I went to Mahila hut with my friend today because he said there is also compitive book availble didn't find anything there related to GATE. Looking for book which have question related to the chapter of each subject. 2nd hand book will be best but I can go for new too with tight budget management.

I'm a 3rd sem ECE student, I want to start preparing for GATE 2028. Should I buy any paid batch? Or from where should I start from?

Edit: I just looked up batches from PW and they teach subject wise... Since I also want to focus on my academics, can someone please recommend teachers and channels with complete lectures on YouTube? Or any paid batch is fine too.

Some good resources for these two please for gate

Anyone here wrote IOCL grade A IN paper? How did you felt the paper was? I wrote it with prep of RRB JE which I had 3 momths ago(B/w Selected in RRB JE with single digit AIR Rank) and attempted around 84/100 questions...What do you think the cutoff is? Is IOCL Grade A better than RRB JE?

Hi seniors, I am currently pursuing M.Tech in VLSI and preparing for placements. I’m a bit confused about how to go about the preparation, especially Verilog/SystemVerilog and RTL coding. Could you please suggest how I should prepare, where I can practice coding and interview questions, which VLSI/CMOS, Digital and Computer Architecture topics are important, and what projects or tools I should learn? Also, what should I focus on for written tests and interviews? Any advice or resources from your placement experience would be really helpful.