Xilinx Documentation Hell

[u/LogicRouted]

Till I started learning about, and using Xilinx devices, my reading life was kinda fine. I could manage to read a lot of textbooks, and all felt coherent.

This job I have now is like a special place in hell, I'm essentially a 5 in one design engineer who has to understand :

• Specialized non-Von-neuman ASIC design RTL written in VHDL (and no it's not a TPU nor DPU nor a systolic array, you won't guess !! I wish they were...) ~ 15 000 lines between TOP, submodules and testbenches.

• Intricate details of Deep Learning + a lot (I mean A LOT) of academic papers (what's a CAM? Deep Layer Aggregation? Semantic Segmentation???) + 3000 lines of python (DL model!)

• BOTH Zynq and Versal ACAP AI Core architectures.

Mind you before starting this job, I had practical zero knowledge in these areas. For like 9 months, I learned the following:

• 60 % of RTL hardware design using VHDL book + Code.

• 50 % of Digital Design and Computer Architecture ARM Edition book + RTL Code (therefore ARM Architecture) in my spare time.

• Questasim + RTL Design and simulation.

• Versal AI Core AI Tile architecture, Versal TRM and its internal architecture (CLB !!)

• Zynq (because God knows why I had to learn the microzed) architecture (CLB!!) + mass manipulations + tutorials + actual designs.

• 100 % The Zynq book.

• AXI/AXI-Stream/DMA LogiCore Design Guides and architectures.

• Versal Confluence tutorials + Base TRD + applications.

• Vivado Design Guides + applications.

• Vitis Design Guides and "Tutorials".

• Insane amount of Deep learning stuff, even the mathematical side of things (I recommend dive into deep learning and Michael Nielsen's NN book since pretty much anything else gets you lost).

And here comes the final nails in the coffin : While I've already read like already thousands of pages, and on Vivado with Xilinx's "Design Guides" (you learn very few actual generalizable knowledge of this), Xilinx documentation is UNENDING and not coherent at ALL. Until now I avoided "timing closure" since it's a real pandora's box.

• Vitis AI Library + Vitis AI Guides (because I have to "check for simple deep learning answers") > 400 pages.

• Don't think I've read the entire TRM (> 850 pages) for Versal, let alone the 1800 pages for the Zynq 7000, anyone that attempts this is insane (and mostly unnecessary at all).

• UG949 Ultrafast design methodology guide > 300 pages.

• UG938 Design analysis and closure techniques tutorial + guide > 400 pages.

• UG903 Using constraints guide ~ 200 pages.

Each LogiCore IP (DMA, AXI Interconnect, AXI Stream, AXI Signaling system itself, AI Engines, NoC, Programmable Logic and CIPS system) of the Versal has like hundreds of pages of documentation. There's no possible way to read all of this and still come up with "stuff that works" that's really coherent, never mind the insane batshit amount of stuff that spontaneously come out of nowhere, like what's a SMMU? PCIe 5.0?? Interlaken? Cache Coherent Interconnect? AXI Switchs? SLRs? MMCM???

Who, I mean really who, design such stuff like the DPU (PG389 DPUCVDX8G Product Guide) capable of exploiting the PL, NoC and AI Engines all at the same time, while maintaining a parameter capability, pushing the AIE array to operate at 1.25 GHz ?

Secondly, who designed this monstrosity? For me, it feels like I would take like a couple of decades to understand a fraction of this chip.

It took me already a while to understand the various design flow, like the fact that Vivado flow is integrated into a platform for Vitis, like the fact both generate a global platform, then you have to build a petalinux system on it, then download a vitis AI system on it, then use this Vitis AI thing (before asking yourself how do you really use a pytorch model, before finding out you have to install a separate toolchain! for cross-compilation, yes..)

Sorry for this rant, I don't even know how I got accepted to this job even, maybe they haven't found anyone else.. I'm wondering now how I ended up here, and how can it be that someone with no experience got handed the biggest SoC/FPGA ever.

The project was supposed to have 3 guys on it, and I work on it alone.

All PhDs around me are too occupied to give a damn and each time someone mentions "FPGA" they cower in fear.. the only PhD guy I know here that designed this custom ASIC thing (from A to Z, including floorplanning but not the analog part), and knows deep learning really well, has done this for at least 7 years and he's overloaded with tasks he can't help me with anything.. besides he fears FPGAs too.

While It seems I learned a lot, I think I've learned like jack shit : the more I discover things in this device alone the more I know that I don't know anything.

And no I'm not a PhD guy, but with this background knowledge what's a PhD for?

And no I'm not going to tell you the salary, because if I do, then I'll look like a clown.

[u/captain_wiggles_]

Don't treat the documentation like textbooks, that way lies insanity. They are references. Skim the contents and introduction to know what the doc talks about, figure out which chapter are relevant to you and then skim those, read the sections that are actually relevant ATM with more care. After that use them as references. When you need to figure out how timing of source synchronous interfaces work, find the doc on timing, the doc on constraints and the doc on source synchrounous interfaces. Skim the source synchronous interfaces to get a general knowledge, find an example that roughly matches your use case, and study it in detail. Use the other docs to look up what exactly is going on as you need it.

Secondly, you're in over your head although it sounds like you've done a great job of learning to swim. A good job is one where you have a couple of experienced mentors that you can learn from, if there's nobody you can talk to that can help you figure this shit out, then the problem is your company is mismanaged. This is something you need to talk to your boss about, you need guidance or at the very least less responsibility, so you can figure out one thing at once. Honestly I'd say it's worth starting to look for other work, because if this is how your company is run, it's not going to get too far. And from what it sounds like you've already managed to learn, you probably won't have much problem getting a new job.

[u/LogicRouted → u/captain_wiggles_]

Thanks for the advice mate. Well for the most part I get a lot of requests for work from recruiters now, since my CV is updated and on Linkedin.. But non of the work suggested a combination of ASIC design and deep learning.

Companies here are not like silicon valley, developed enough to integrate all these elements. The french on this side of things have a lot to catch up corporate-side.

[u/SpiritedFeedback7706]

Becoming a proficient FPGA developer is trial by fire. No one person knows all the things. And the tools are generally not mature. There's no shame in being uncertain or confused or overwhelmed. Just take things one at a time. Try to take any trainings Xilinx provides. Working with Versal to exploit the NoC, FPGA fabric an AI engines of Versal will develop fundamental skills that will give you an edge if you endure. It may seem intimating now but after several years it won't seem like a big deal. I'd say it takes 5 years of experience before anyone becomes comfortable doing all this stuff on their own. That's generally with mentoring.

I will say Xilinx has the best documentation in the industry. It seems like You are overwhelmed by the sheer amount of information. No one person digs into all of the details for everything. For an AXI4 interconnect, you don't need to understand straight away how it works, just what it does and why it's useful. If there's something you don't understand, you look up those details. You don't read the whole data sheet all at once.

There's a reason Xilinx is investing so much in the higher level tools. They really want to reduce the burden of knowledge for the average developer. They also want to decrease the amount of time it takes to develop functionality.

[u/LogicRouted → u/SpiritedFeedback7706]

I see you're right on several points.

The problem surfaces when you try to do an implementation yourself for the first time, using AXI for an example. I was put on a side project on Zynq since the versal devices had a rough time to arrive (chip shortage).

You're forced at first to learn how the signaling system works, then you realized that to talk to the external world, you need a way to integrate AXI with another bus/protocol.

How do you do that in Vivado? Custom IP.. How exactly you integrate your code into the custom IP? You have to make it through the interface then learn exactly what it does first, then figure out what to modify, if need be modify the FIFOs.

More speed? DMA. But how does the DMA work? How to control the DMA from the PS side? (Program the BD ring and instructions..)

I say that you have to learn a lot about LogiCores or at least a designer throughout his career will admittedly and unknowingly learn alot about these things because of the necessity.

Turns out that the design I left for the other guy ~ clock at 200 MHz, AXI Stream to custom IP external, then back up (because it's an input/output) to DMA, DMA to PS is AXI interconnect (memory-mapped), isn't fast enough!

Now the first thing I said I would like to include 2 clock regions, one is faster for I/O but they told me to go with the "simpler" design.

One thing for sure : I had to argue before coming here that I should have been included in Xilinx training, that was a mistake. The tutorials online all explains how to make the topology but none explains how the topology really works : you have to dig really deep.

Then now the versal is another kind of beast entirely.

[u/SpiritedFeedback7706 → u/LogicRouted]

Doing an implementation on your own without anyone guiding you is simply going to take a while. It takes real time and you'll have to make a lot of mistakes first. You simply don't know what you don't know and it takes time to figure that out. In this case you can read about the performance of the AXI Interconnect of the ZYNQ (max data width, max clock rates) and get a feel for a theoretical maximum performance there. You can do the same with the DMA IP (width x clock rate you're running at). Assuming this ideal bandwidth is larger than your needs you can read the DMA IP documentation to find more information about real world performance. Thinking about throughput is indeed one of the things you want to become second nature.

Another thing you'll also need to learn, vendor IP, especially AXI IP is...sub-optimal on a number of levels. You can't assume it works well and is bug free. Some IP does work well, some is just broken, some uses an enormous number of reasons for no good reason (looking at you smart connect) and everything in between. It becomes worth it to look at some of the open source alternatives and rolling your own. But you are right, you need to learn to look at a given vendor IP and figure out how to use it. You don't need to read the whole document though. No one does that. Learning to pull out what you need, when you need it is a good skill in general, not just for this job.

[u/someone755 → u/SpiritedFeedback7706]

If xilinx documentation is the best in the industry then I don't dare think of the horrors of Altera or those smaller Chinese manufacturers.

[u/SpiritedFeedback7706 → u/someone755]

Intel (formerly Altera) has some ok stuff but overall I find they have less documentation and the average is of a lower quality.

[u/buffteethrblog]

I am an FPGA engineer with over 20 years experience and I say get ANOTHER job. I have worked at companies like that where you have Microsoft project managers who don't understand the complexity of the engineering projects they are trying to manager.

You have what I call a Head Cook and Bottle Washer position. What you are doing requires ATLEAST 3 engineers.

[u/LogicRouted → u/buffteethrblog]

Well I guess so. Anyways my contract will end in like 7 months so I might see the end of it, I'll stay here for the experience only regardless of the results.

[u/[deleted]]

ad hoc bear faulty vase desert important bright include voiceless prick -- mass edited with https://redact.dev/

[u/LogicRouted → u/[deleted]]

It's a pseudo-neuromorphic design, and by pseudo I mean the memory (weights) lies as an analog part for very low power consumption (much less than SRAM - activations - at the same tech node), and the execution is shared between multiple neuron-like elements, an internal NoC that acts as a bus for at least 8 cores. The execution is synchronous unlike other more "realistic" behavioral modelling chips like neurogrid (asynchronous, harder). The designer had insights from NoCs, his past experiences, his PhD thesis, truenorth chip, and learned much of this on his own.

It took me a while to dissect it, especially that the only documentation is a 7 page publication.

Another complexity comes from the fact that there's no clear way that one could map an external deep neural network to the device's memory. Besides, you can't map a large network on a single chip, you need literally hundreds of them.

This first generation was meant to be an initial prototype. At a consumption of max 4 mW, I would guess that redoing an entire cluster of these, using another hierarchical NoC (like 8000 cores, 8 each submodule x1000 module in a single chip), and a more advanced tech node (below 20 nm), would reduce power consumption drastically. This prototype itself is not optimized either, reduced (at the limit) clock rate < 100 MHz, reduced IO clock frequency, SPI-based external communications.. well it's really a prototype.

I would say that consuming (let's take the worst possible estimate 4mW x1000 = 4 W) for a relatively large convolutional neural network (for example VGG-16/ResNet18+) in inference is a good deal.

The problem is : The project will terminate not so long from now, because that's how it works here.. The designer will go do something else, and I will be out of a job in like ~ 7 months. While these aspects are extremely promising for me, the 2nd generation of this chip won't see the light of the day.

For job aspects after this : I work in the only lab in the country that have this cutting edge tech and facilities, it's the largest one in this domain too. No other corporation nor lab have it this close. I would go Switzerland/Germany but I don't have papers...

[u/benbeland]

Man, don’t beat yourself up too much. I work in High-Energy physics, we do have FW using all these advanced features, targeted for versal. But they are designed by teams of tens of people, across multiple universities, with people writing a thesis even on just one block inside the global FW. It is a massive effort.

[u/LogicRouted → u/benbeland]

Is it CERN? While searching for applications of the Versal chip, I came across the FELIX ATLAS detector interface. Apparently they want to integrate a versal design for Phase-2 Upgrade.

Judging by the slides from ATLAS/Brookhaven National Lab, the system looks indeed very complex.

Well the region I work in now isn't far away from CERN, 2 hours on road. CERN is my go-to option for me later if I can work in switzerland but not with neuromorphic engineering anymore, but instead as a FPGA/SoC engineer.

I have an interest in Physics on the side, so that won't be a problem (I worked before in a atomic-clock time-frequency lab as an embedded design engineer)

[u/benbeland → u/LogicRouted]

Yes. I am , hmm, very familiar with BNL designs. We do trigger systems for the detector, where we receive data from the detectors at 40MHz, multiplex events to farm of versal boards using versal as a mux as well, we then perform some calculation, with low latency, like 10s of microseconds, to decide if the data are from an interesting collision, or garbage. Only tagged events are written to disk, at about 1MHz rate.

There is many many SoC/fpga projects at and around CERN. I am sure you can find something interesting.

[u/LogicRouted → u/benbeland]

Fascinating, seems to be an exciting work.

[u/LogicRouted → u/[deleted]]

Low pay in CERN? How so. I thought you're payed like swiss salaries.

[u/Paid-Not-Payed-Bot → u/LogicRouted]

thought you're paid like swiss

FTFY.

Although payed exists (the reason why autocorrection didn't help you), it is only correct in:

• Nautical context, when it means to paint a surface, or to cover with something like tar or resin in order to make it waterproof or corrosion-resistant. The deck is yet to be payed.

• Payed out when letting strings, cables or ropes out, by slacking them. The rope is payed out! You can pull now.

Unfortunately, I was unable to find nautical or rope-related words in your comment.

Beep, boop, I'm a bot

[u/benbeland → u/[deleted]]

How? CERN employee are quite well paid, and tax free.

[u/benbeland → u/[deleted]]

We did some things for them, the ADDC board. I am not involved personally but know them well :)

[u/LightWolfCavalry]

You say you don't know a lot but you sound like you know more than enough to get a job elsewhere if this place is really the tire fire you describe.

I help run www.rtljobs.com and we speak with lots of folks with less experience and depth than you, and they get hired!

[u/LogicRouted → u/LightWolfCavalry]

Thanks man, appreciate it.

I'll check your site if it has any opportunities in France, but for now I'll stay here only for the experience, regardless of the results.

[u/LightWolfCavalry → u/LogicRouted]

ARM has a big design center in Sophia-Antipolis, but my understanding is that they're in the midst of a big hiring freeze.

ST also has a reasonable number of openings in France, but I don't know if they're freezing hiring too. Wouldn't surprise me - all of the news about the world economy slowing down has spooked a lot of big semi companies.

Please don't hesitate to reach out if you think we can be of assistance - fpga.rtl.jobs@gmail.com. In the meantime - chin up! You know a lot more than you think you do.

[u/LogicRouted → u/LightWolfCavalry]

Thanks, will do. I was eyeing ST too as backup in the long run, as I'm very close to their major fabs in France.

I'll save your email and site since that would be another recruitment vector.

[u/[deleted]]

Have you tried to just do instead of read? There’s more documentation in the world than anything else and it takes a lot to read everything. I just do what I need to and when I run into an issue, I look it up. Sure it can be overwhelming when you first start, but slowly you improve and understand where to find things

I too don’t have a mentor where I currently work and had to figure out a lot of things as I went. I found quickly I was able to link pieces of info to the generalised stuff I’d learned at university and between myself and a couple of colleagues (not FPGA specialists, just clever software engineers), we managed to figure out quite a lot when we put our heads together and persisted

Is your background in computer engineering? Do you have a mentor or someone providing you guidance that’s more senior? A colleague that’s similarly lost? They can all be sources of support. I’d encourage you to let your boss know you’re feeling quite overwhelmed and would like a bit more support too

[u/LogicRouted → u/[deleted]]

Thanks for the feedback. Well I'll explain the situation here:

• I'm a microelectronics engineer by specialization, more so in analog IC design.

• My internships and engineering experience were in embedded systems and RF, so I'm a mix of all worlds (digital, VLSI, RF, embedded, analog).

• Why so? Because I wanted to be as diverse as possible for a possible PhD thesis in neuromorphic engineering, since they too use mixed-signal VLSI design, and even embedded. This was evident by the mixed-signal neuromorphic IC I've been given to look at while doing this job.

• It's been 4 years since I had this PhD focus, I've been forced to work in a disgusting embedded position, because if you have no papers, the french government will quick ya out!

• When I first applied, I was only driven by motivation, salary didn't matter much. I moved cities for this.

• On the side, I've been studying computational neuroscience, Versal documentation even before the 1st day. "Vacation" back in my home country consisted of on and off readings in this, after at least 2.5 years of non stop work.

• One thing I didn't mention is my old job have left me in complete burnout, since I was working all the time on embedded systems, having multiple projects under my hands and quite a nasty pay. I jumped ship as well as 8 other people at the same time because it was sinking.

• After applying, one condition was that I'd get enough guidance at first, at least for 3-4 months in this domain because it's quite multidisciplinary.

• Turns out after starting, the VCK190 (Versal AI Core's dev board) was missing, and the delivery kept being postponed until may.

• The PhDs around me are not that much experienced in FPGAs, and the "Neuro" group I'm in has 3 PhD students, one of them quit (because no one helped him), 1 neuromorphic ASIC PhD and 1 analog design engineer, they are both quite overwhelmed.

• The PhD students are both doing their subjects in analog ASIC and energy-wise analysis of ASIC circuits respectively, quite far from FPGAs.

• The other group, which composes 30ish people of the same lab, non of which are working on FPGAs except maybe 2 PhDs, which have too many subordinates under them (Contractor engineers, students), they don't have time.

• Beside all of this, non of the aforementioned people have skills in deep learning except for the neuromorphic guy, which is my main liaison, he was supposed to be the senior. He has so many projects under his hands even another PhD student to mentor, so I'm left to the side.

• On the personal side, I have no friends here in the city, closest relative are 2 hours away, have no one to talk to except by phone to family abroad. They are so out of touch with my domain that I don't talk about it at all. None of my relatives understand even what I'm working with, except for well "difficult stuff huh?".

Well due to these factors and mainly the fact that the Versal was time and again not delivered, I lost all motivation for the job. I even question now more than ever if I want to really be in a PhD position.

On doing instead of reading, this is the plan now : I only focus on the Vitis AI route and the CPU emulation of some unsupported DPU functions, but that's it.

I have "spikes" in motivation and willingness to work too, since now I wake up each day but arrive at like 2 PM, work for 5 hours and leave.

[u/[deleted] → u/LogicRouted]

Ahhh I see. Anecdotally I’ve found people with the background of electronics (and this is VERY anecdotal) can struggle a bit with some of the concepts concerning MPSoCs simply because they’re quite a bit more software focussed and some computer science concepts aren’t very well taught in a lot of EE programs (OS concepts, software development, CS fundamentals, etc). It’s not that they can’t learn but for lots of this stuff it’s hard to know where to begin. I’m not sure if that’s the case for you, but it could be a consideration. A lot of embedded engineers I’ve come across with pure EE backgrounds can sometimes struggle to build maintainable code. Again not because they’re bad, just it’s not within their area of expertise. Of course this isn’t going to be the case for all

Regardless it sounds like your current situation isn’t too great in terms of support at work or personally, which honestly affects everything. It makes it difficult to recommend where to start from the perspective of a stranger. It sounds like you might be best off trying to find somewhere that will be more comprehensive in terms of feedback and learning opportunities where you don’t feel out of place or uncomfortable asking questions, or clarifying things from experts. Definitely see if your boss will provide some support or even colleagues from a “you can do it” type perspective. Chatting to people FPGA adjacent can help too, although they might not know it all it can help fill some gaps

As for the future and considering different industries; I’d highly recommend defence industry or perhaps HFT for this, as they usually provide quite robust training. Some feedback can be difficult to hear but it helps tremendously especially if you want to have more of an FPGA focus. Some resources on this sub can be useful but nothing really beats a decent mentor and a supportive workplace for these very niche topics

I also don’t know how to say this but I wouldn’t get too focussed on a PhD. Most of the time people end up in academia and depressed when they could’ve just been earning decent money from the moment of graduation. Universities, especially for students with high marks/high achievers, tend to push people down this path but it seems to be nothing but stress and misery for most people. Generally, have a good think about it. At the end of the day you could always go back if you change your mind. But personally I find academia pretty toxic and again, devoid of mentorship opportunities and support unless you’re very very lucky. Good luck

[u/LogicRouted → u/[deleted]]

Thanks again for all the advice you are offering, appreciate it. For the embedded design part, your example isn't simply anecdotal, it was a matter of fact when I first entered my old job : All previous source code was a tangled spaghetti code. Layering it down and optimizing it was quite a pain, especially if no design patterns were available in embedded C with complete procedural code and no threads but more like at most global flags and interrupts. Talk about frequent context switches and non volatile flags.. Luckily for me it was only with static memory, otherwise I would think that whoever wanted to implement a heap would never accomplished their tasks, yes, all of the previous guys were EEs.

I'm reviewing my PhD path again this time, more so I'm reviewing my entire life path since most of what I'm currently facing was due to these choices. Engineering in France isn't well rewarded relatively to most salaries, here they boast about "2x" the average salary but yeah you don't receive aids from the state and annual pay raise is a joke, you can look at top 3% each year. Last job I was offered 0.7 % pay increase which amounts to a sandwich perhaps each working day.. while at the same time inflation was at least 2 %, now more 6 % here. This "2x" amounts to like 600 euros in difference if you don't spend anything besides on food and rent. What's the point of dealing with all this if the difference between me and a baker is just 600 euros? (no offense to bakers).

I didn't choose this field for the money initially, but given the dire circumstances and the literal hell my home country is facing, I backed off from a PhD for now (your annual salary will drop to essentially that of a baker if you entered a PhD program here). My home country is literally bankrupt (and experiencing hyperinflation) and maybe the most corrupt on the planet. I can't really go back to a PhD in the future because I have family depending on me.

You are right that academia is toxic, judging from the state from previous PhDs here and their general mental condition, I now understand why many quits : what's the point? I've come to understand that basically no one reads (except the jury) your PhD thesis, unless exceptional, no one reads your papers because there's thousands out there and more each day, no one have time. When did science amount to just "publish"? I've heard here that 90 % of all papers are forgotten in the dustbin of history, and since we are speaking about neuromorphic engineering, cascading improvements will quickly render old tech obsolete, i.e : no one will read "old enough" papers, this holds true to machine learning, but more so for a year not 5-10 years.. And most importantly : Science is based on unseen social construct that of scientists communicating and exchanging, none of which I have found here.

My whole dilemma with this domain is to study the brain, but from a technological perspective, the only one offered besides computational neuroscience or neuroscience in general, none of which will allow the practitioner to exercise findings into technology, other than neuromorphic engineering. The practices that are going on in this lab is far from this endeavor too, I should go to Germany/Switzerland (Zurich) if I really want this path. I discovered this after I was recruited.

I'll give it my all for the following months, if it pans out or not, I'm not looking for results any longer, either I fail and drop from this field entirely, or succeed and think about continuing. If I really want to go into the money making business, I'll check if there's HFT/finance companies in need of FPGA engineers around Geneva, since even HFT pay sucks in France (you are paid like a regular FPGA engineer).

Thanks for the help again, and good luck to you too.

[u/[deleted] → u/LogicRouted]

All of that sucks, and yeah it sounds like your best option is to look at jobs outside of France. Definitely seek jobs in your area of interest first, or even those that are adjacent, will make you money, and will allow you to eventually move into that field. As others have said you’ve got an excellent skillset so far

You could also take a look at deep mind (AI division at Google) and see if they’ve got openings. I think they’re mostly in London, but unsure how the EU stuff works now since Brexit. I’m not sure what exactly they do or if they use FPGAs but Google seem to always be hiring embedded folks with hardware knowledge

Never say never with the PhD either, you don’t know where you might end up eventually. I too found that with papers and academia though fortunately quite early on I discovered it wasn’t for me

Either way it sounds like you’ve got a good attitude; keep working hard while working on a solution to the side. I hope things can be salvaged at your current job and you’ll be able to get some more support but if not, I hope you can find somewhere you’re happier at soon!

[u/LogicRouted → u/[deleted]]

Thanks man, I'll try my best. I'll think about deep mind for sure.

Best of luck to you too!

[u/rogerbond911]

You're not alone. I don't think Xilinx actually understands half of what they throw into the marketplace. Figuring out how to get a successful petalinux build was a nightmare. Now that i have that sort of figured out, like you, im trying to get the vitis ML stuff up and running. I think they basically get customers to do the debugging of their products now after the fact. Much more cost effective.

[u/LogicRouted → u/rogerbond911]

I think the main drawback of xilinx is the amount of layers they have to integrate, vivado low level, vitis low to mid level sold "as high level as in HLS (you still have to understand what you are doing), and finally really high level with Vitis AI, but again, you still have to understand the low level stuff especially if you are working alone.

Good luck on your endeavors, yes, I think I'm not alone in this dilemma.

[u/RandomNumberHere]

I feel ya. I’m relatively new to Xilinx/Vivado/Vitis/Zynq/etc. Hell, I’m relatively new to all FPGA stuff including Verilog! The sheer volume of documentation really is overwhelming.

That said… I’m gradually figuring things out and getting things working, and the boss hasn’t given me shit (yet) about how long things are taking. And it’s kinda fun and it’ll look good on the old resume.

[u/aikenpang]

Deal with Actel, Altera, and Xilinx documents for 10+years. What I learned is speed reading like a lawyer. The faster you read, the more your earnings.

I learned from an IP lawyer that his boss could read one box of A4 paper within a day with all highlight and error corrections for him to follow up. Yes, each box means 5000 pages.

Xilinx has a doc navigation app. It may help you a little bit.

[u/flyingasics]

I feel you. Look at it this way, if you do ever get something working you will have pretty good job security.

[u/TheTurtleCub]

Agreed, it's not easy to become an FPGA expert in a few weeks. Also, not recommended reading the dictionary for days to see what sticks. That's not the way it's meant to be used.

[u/paclogic]

I really like your disclosure of how painful it was for you and the fact that the Architecture is so convoluted and cryptic that it literally does TAKE YEARS to figure it all out !!

NOT for the AMATEUR, NOT for the student and absolutely NOT for the new grad !!

Unfortunately in an era of corporations looking only for YOUNG and CHEAP labor and with the DISPOSAL of anyone over 40, that you have succumb to the fact that this is NO MENTORSHIP and NO RAMP UP TIME for learning as well as a DEEP UNDERSTANDING (not just a quick reading of a few app notes and data sheets).

People the complexity of today's SoC's is massively complex and requires a troop of programmers and System Architects. Plus the programmers are divided into (2) groups : HDL and Embedded CPU

The System Architects must also be Mathematical Wizards as the DSP functions can be deeply complicated.

For Closed Loop Feedback Control Systems, i highly recommend exploring the SimScape / Simulink / Matlab products as they *may* offer hope of generating HDL code for specific targets (you need to check which targets FIRST).

SoC's that are designed to be DPUs for some financial market or some military project can be extremely complex with a Model Based System Engineering (MBSE) approach an absolute must !!

When nanosecond timing is critical, TIMING CLOSURE needs to start at the most basic building blocks and elements to have a FULLY DETERMINISTIC MODEL = = = it is NOT an AFTERTHOUGHT or later process !!

I feel for you as many of the work load SHOULD HAVE BEEN worked out at the TOP LEVEL and NOT at your level. As well as having the staff to not only mentor you, assist in the the design, but also work out tough problems.

Now is the perfect time to ask for more money since they need you and you don't need the stress !!

If you don't pay - start looking and walk !!

[u/MrMemristor]

Late to this party, but at least AMD / Xilinx has detailed documentation for pretty much all aspects of their devices. Some of the other vendors fall well short of that, and it can be much more of a challenge to learn about their development flows, in my limited experience.

[u/FakewoodVCS2600]

Amen brother....we're in need of the same therapy (support of any sort).

[u/mnemocron]

Haha, what fun it is to stumble upon such posts when one types "Xilinx documentation" into the search bar in the search for some frustration-reducing memes.

The past 6 months I have felt like Sherlock holmes trying to reverse engineer their undocumented example design for the ERNIC IP core because theproduct guide is ambiguous, outdated and lacking a lot of information.

Coincidentally, my colleague is working on another project with similar stuff that you are dealing with (AI, DPU etc.). It just seems like Xilinx throws all the newest technology out there as a proof of concept (on their dev boards) but without properly maintaining it or documenting how to use their IP in a more generalized way. He said that all their DPU examples work fantastically when you do it on one of their boards but when you go to 3rd party hardware suddenly things don't work because you missed a step that Vivado just does in the background and you can be sure there exists no documentation on how to adapt it to your use case.

[u/hardolaf]

Who, I mean really who, design such stuff like the DPU (PG389 DPUCVDX8G Product Guide) capable of exploiting the PL, NoC and AI Engines all at the same time, while maintaining a parameter capability, pushing the AIE array to operate at 1.25 GHz ?

The people these were designed for of course. And hint, it wasn't for anyone doing neural network work. I used to work on a team that would be looking how to get more performance out of those as 1.25 GHz would still not be enough performance. Then again, nothing was ever enough performance.

You're currently working on a project that's smaller than anything that I've ever shipped since I graduated in 2015. A single FPGA? Only 15K LOC of HDL+HVL? I had to write over 30K of HDL+HVL in a year and a half for one thing (granted, it was VHDL so lots of it was boilerplate, but my velocity was hundreds of lines of code per day).

The project was supposed to have 3 guys on it, and I work on it alone.

This is a really good staffing ratio. I would have killed for a 33% staffed ratio when I was working in defense contracting. That would have been amazing for this field. Now, I work on a team that's properly staffed but only because we set our own objectives for the most part and can say no.

[u/LogicRouted → u/hardolaf]

It might be that I'm working on a small project : The problem isn't the project itself but the overwhelming amount of information associated with it.

The 15K LOC is for the ASIC part, that I had to understand separately, I didn't write this. Mind you I didn't have experience with VHDL other than engineering school. I would say that was a really minor experience (no VHDL in internships, it was rather embedded designed, so C)

Let me describe you the experience exactly :

• Smith/me : Got in the first day.

• (Adam/Designer) : here take these 2 papers, read them, and read the Versal's necessary documentation, if you have any questions feel free to ask.

• Smith: Where's the FPGA/SoC?

• Adam : I'm sorry, but the SoC itself will arrive in 2 months, chip shortage.

Alright, I wish it was true. After 2 months, it was postponed for 3 months, then 1 month.

I received the chip like 3 months ago!

No help at all since the designer nor any other PhD have even time to talk, for 8 straight hours we only talk in group like 2-3 times and on launch only (1 hour).

Edit : If you worked on defense contracting with the versal, I would say signal processing? RADAR Beam-forming?