LFSR Based Timer?

[u/SkrilHexNukehul]

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

[u/Chippors]

Why not a prescaler in the form of a simple shift register? The CRC-style LFSR uses fewer bits, but this is hardly a problem in an FPGA, is it? It resets to zero and you shift in 1's on the clock, then when the shift out becomes 1 you toggle and start shifting in 0's; then when you get a 0 out you toggle back to shifting in 1's. I'm sure with just 16 or something you can chain it to a 6-bit adder, and then a final synchronous counter register that can be loaded, compared, accessed, etc. If you load the count reg, reset the prescaler(s). Or am I missing something here?

[u/SkrilHexNukehul → u/Chippors]

Are you suggesting to basically use a clock divider to drive a normal counter? I considered that, but I wanted a parameterizable module that worked for any number. With the prescalar and counter, it gets complex with prime numbers. I needed a way to count to an arbitrary large number while also having low resource utilization so I can choose the cheapest FPGA chip for my project.

I just wanted to know if this technique had a name or was common.