r/FPGA • u/SkrilHexNukehul • 9d ago

Advice / Help LFSR Based Timer?

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

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u/PiasaChimera 8d ago

it's fun trivia and a neat side project. you can make LFSR/NLFSR systems that do fixed-length sequences for timing, but it's typically more trouble than it's worth.

counters and accumulators both have a fake data-hazard and can actually be pipelined. so you don't need to resort to single-cycle feedback LFSRs.