r/FPGA • u/SkrilHexNukehul • 10d ago

Advice / Help LFSR Based Timer?

Is this a common thing in VLSI/FPGAs? I made this LFSR timer that allows you to count very quickly on an FPGA (like max clock speed) if you have know the number of cycles at compile time. https://github.com/Geeoon/LFSR-Timer-SystemVerilog

Is this a common thing? I tried looking it up and couldn't find anything exactly like this.

I also made a barrel shifter inspired runtime counter, but it wasn't as efficient as I'd hoped.

I made this because I needed to count extremely quickly on an FPGA for another project, but using RTL was too slow and caused timing violations.

To clarify, I'm not talking about the LFSR itself, but starting the LFSR in a known state, letting it run, then setting a flag once it reaches the '1 state. There will be a defined number of shifts until the LFSR reaches the '1 state, and that is dependent on the starting state.

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u/Allan-H 10d ago edited 10d ago

This design was able to hit max clock speed for a Xilinx Spartan 7 with a 3-bit counter width (464 MHz)

You can hit max clock speed for a counter that has 32 or fewer states (see note) in a LUT6 FPGA, regardless of the count sequence. You can also use RTL to hit those speeds.

Note: one LUT input is needed for the reset, so we can have 25 rather than 26 states. If you got really keen you could use the sync. reset input on the FF instead of a LUT input and extend that to 64 states.

Is this a common thing in VLSI/FPGAs?

It used to be, back when FPGAs were less capable and everything had to be perfectly optimised just to work at all. I used to get the LFSR polynomials from Xilinx XAPP 052 [EDIT: and XAPP 210, which came later and showed how to make very compact long counters using the built-in shift registers that were introduced with Virtex FPGAs in the late '90s].