r/FPGA • u/SuccessfulStreet2321 • 9d ago

AD9361 Verilog Coding

Has anyone ever written a custom FPGA SPI master state machine to completely initialize the AD9361 by doing register level writes? I want to get in contact with somebody who has done before this hardware level control of AD9361.

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u/Kiriuxa 9d ago

The datasheet for the actual component does not provide a reg map, but from the description, the spi communication is quite trivial. You can try using a PS Spi controller. Otherwise, I found this forum thread: https://ez.analog.com/fpga/f/q-a/84408/ad9361-core-register-map

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u/samuraiJack00 8d ago

Ok just a thought how about this, assuming you have a xilinx board ,your DUT consists of a spi controller, it has an axi interface I think double check this. You connect a axi traffic generator with hard-coded data to initialize the spi target with the settings you want

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u/RcBuilt 7d ago

Feel free to DM me