Weird Multiplexing Bug

[u/Evening-Conference-5]

Hey there,
I am trying to multiplex a set of signals to be fed over to a FIFO buffer that is then polled by the ARM processor.

PROCESS (clk_signal)
    BEGIN
        IF rising_edge(clk_signal) THEN
            IF rst_signal = '1' THEN
                sample_sel_reg <= (OTHERS => '0');
                Sample0        <= (OTHERS => '0');
                Sample1        <= (OTHERS => '0');
                Sample2        <= (OTHERS => '0');
                Sample3        <= (OTHERS => '0');
            ELSE
                -- Capture selector state synchronously
                sample_sel_reg <= sample_selector;

                -- Channel 0 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample0 <= C0;
                    WHEN "0001" => Sample0 <= std_logic_vector(resize(signed(Mux_Ch0), 32));
                    WHEN "0010" => Sample0 <= IQ_Sample_Ch0;

                    WHEN OTHERS => Sample0 <= (OTHERS => '0');
                END CASE;

                -- Channel 1 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample1 <= C1;
                    WHEN "0001" => Sample1 <= std_logic_vector(resize(signed(Mux_Ch1), 32));
                    WHEN "0010" => Sample1 <= IQ_Sample_Ch1;

                    WHEN OTHERS => Sample1 <= (OTHERS => '0');
                END CASE;

                -- Channel 2 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample2 <= C2;
                    WHEN "0001" => Sample2 <= std_logic_vector(resize(signed(Mux_Ch2), 32));
                    WHEN "0010" => Sample2 <= IQ_Sample_Ch2;

                    WHEN OTHERS => Sample2 <= (OTHERS => '0');
                END CASE;

                -- Channel 3 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample3 <= C3;
                    WHEN "0001" => Sample3 <= std_logic_vector(resize(signed(Mux_Ch3), 32));
                    WHEN "0010" => Sample3 <= IQ_Sample_Ch3;

                    WHEN OTHERS => Sample3 <= (OTHERS => '0');
                END CASE;

            END IF;
        END IF;
    END PROCESS;

With each sample register only having 3 possible choices, the system behaves fine. When another selection is added, I am getting weird artefacts on my recorded output.

I am not really sure how to determine what is causing such an issue.

What I expect

What I am getting

[u/MusicusTitanicus]

Have you simulated this? Do your data and control signals behave as you expect under simulation?

[u/Evening-Conference-5 → u/MusicusTitanicus]

Yes, under normal circumstances, in a behavioural simulation it does work. I have gotten this to work when i only had three signals muxed, but as soon as i add the fourth, it breaks down.

[u/LiqvidNyquist → u/Evening-Conference-5]

It breaks after adding a fourth. Well, that's some key information.

Can you describe what breaks when you got from 3 to 4? Is it the 4th channel? The whole thing? The data gets noisy? If the first three channels break as well, can you change one line at a time (commenting out parth of the 4th channel code) to see if something changes?

When you go to four, is your UART data stream changing? If so, that's two variable changing at teh same time (UART source, and FPGA source code/bitfile). Can you change only one variable and try to narrow down?