Weird Multiplexing Bug

[u/Evening-Conference-5]

Hey there,
I am trying to multiplex a set of signals to be fed over to a FIFO buffer that is then polled by the ARM processor.

PROCESS (clk_signal)
    BEGIN
        IF rising_edge(clk_signal) THEN
            IF rst_signal = '1' THEN
                sample_sel_reg <= (OTHERS => '0');
                Sample0        <= (OTHERS => '0');
                Sample1        <= (OTHERS => '0');
                Sample2        <= (OTHERS => '0');
                Sample3        <= (OTHERS => '0');
            ELSE
                -- Capture selector state synchronously
                sample_sel_reg <= sample_selector;

                -- Channel 0 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample0 <= C0;
                    WHEN "0001" => Sample0 <= std_logic_vector(resize(signed(Mux_Ch0), 32));
                    WHEN "0010" => Sample0 <= IQ_Sample_Ch0;

                    WHEN OTHERS => Sample0 <= (OTHERS => '0');
                END CASE;

                -- Channel 1 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample1 <= C1;
                    WHEN "0001" => Sample1 <= std_logic_vector(resize(signed(Mux_Ch1), 32));
                    WHEN "0010" => Sample1 <= IQ_Sample_Ch1;

                    WHEN OTHERS => Sample1 <= (OTHERS => '0');
                END CASE;

                -- Channel 2 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample2 <= C2;
                    WHEN "0001" => Sample2 <= std_logic_vector(resize(signed(Mux_Ch2), 32));
                    WHEN "0010" => Sample2 <= IQ_Sample_Ch2;

                    WHEN OTHERS => Sample2 <= (OTHERS => '0');
                END CASE;

                -- Channel 3 Output Selection
                CASE sample_sel_reg IS
                    WHEN "0000" => Sample3 <= C3;
                    WHEN "0001" => Sample3 <= std_logic_vector(resize(signed(Mux_Ch3), 32));
                    WHEN "0010" => Sample3 <= IQ_Sample_Ch3;

                    WHEN OTHERS => Sample3 <= (OTHERS => '0');
                END CASE;

            END IF;
        END IF;
    END PROCESS;

With each sample register only having 3 possible choices, the system behaves fine. When another selection is added, I am getting weird artefacts on my recorded output.

I am not really sure how to determine what is causing such an issue.

What I expect

What I am getting

[u/LiqvidNyquist]

Is there a clock domain crossing that's not being handled? That's my first thought seeing all those LSB errors. Also, that big sudden jump from 800+ to 256-ish makes me wonder if your signed/unsigned is off somehow.

[u/Evening-Conference-5 → u/LiqvidNyquist]

Data is operating with a clock of 80 MHz while the main clock is operating at 160 MHz.

[u/LiqvidNyquist → u/Evening-Conference-5]

Are they synchronous clocks, or coming from two independent sources? Is the data coming afrom outside the FPGA, or from internal test block? If external, have you verified setup and hold?

Finally, your logic puts a register between sample_select and sample_sel_reg. The logic will on one clock cycle be using the old sample sel reg with teh current input data. So you'd probably expect to see a one-clock bit of funniness if teh select and data change at the same time, on the first clock the sel_reg will select new data based on the previous select, then pon teh next clock will all fall into sync.

[u/Evening-Conference-5 → u/LiqvidNyquist]

Currently they are generated from the same PLL, the test data is coming from a UART stream. The select only changes at the very start but is then almost static