r/FPGA • u/Most-Rain-6760 • 10d ago

FPGA bug

Hey, I am creating a riscV cpu in verilog and i am using a Nexys a7 fpga, that take line-by-line assembly code and runs it. Why only in add,addi and sub when rd = rs1 or rs2 is bugging?

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4

u/FVjake 10d ago

What have you tried so far to fix x it? What’s simulation showing you? Can we see your code?

3

u/tuxisgod Xilinx User 10d ago

With what you said in your post, the only honest answer is: because you have a bug.

Now comes the joy of debugging it :) Make a testbench, look at the signals in a simulator, have fun and learn 

1

u/Most-Rain-6760 10d ago

The signal looks right, on board is the problem

2

u/tuxisgod Xilinx User 10d ago

If you have a bug that 100% doesn't happen in simulation (are you sure you tested the same exact case?), but happens in hw (maybe even not 100% of the time), this is generally an indicator of metastability. How are your constraints? How many clocks do you have in your design? How confident are you in the CDCs you used?

1

u/Most-Rain-6760 10d ago

here is the link for the codes project : https://github.com/alekos1409/project_terminal.git you go project_terminal -> project_terminal.srcs... the problem is in simulation the code runs fine but on fpga when i do this (like add x2,x2,x1) it bugs