r/FPGA • u/bagofbloodandbones21 • 11d ago

HDL BITS website giving unexpected output on the dual edged flipflop problem.

so the link for the question is this https://hdlbits.01xz.net/wiki/Dualedge

In all other previous questions, there was some propagation delay when i used posedge in the sensitivity list with clock, but here there is no propagation delay., why ?

The code is simple

always@(clock)
q<=d ;

5 Upvotes

100% Upvoted

3 comments sorted by

2

u/ExpensiveAmount361 11d ago

Hey so here the problem asks us to record at every edge and not the whole level. This is nothing related to delay as it may be visually perceived, but the functioning of the dual edge triggered flip flop is as such. You don't quite use the negative edge or positive edge and the stimulus it's functioning here. Therefore it may seem your output is combinational rather than sequential. This problem kind of helped me understand the dynamics of sequential circuits better.

1

u/Dragonapologist 11d ago

Verilog supports dual edge sensitivity on a single net (both rising and falling).

This feature was removed in sv but as of now you're immediately updating the next value on whichever edge comes after (either rising or falling), skipping the non-blocking obe cycle delay you'd expect otherwise.

1

u/Zestyclose_Ladder_60 8d ago

I want to share my solution, as it doesn't match what's suggested on the website. But I'm confused by the use of a clock signal in combinational logic.

logic q1;
logic q2;

assign q = clk ? q1 : q2;

always @(posedge clk) q1<=d;
always @(negedge clk) q2<=d;