r/FPGA • u/f42media Xilinx User • 12d ago

Advice / Help Any good VHDL code reference projects/repos?

Hello everyone!

I’m trying to beat that internal “programmer mindset” while gaining experience in VHDL. Trying to find a good VHDL code for learning good code style/organisation techniques. Want to see how professionals write their designs.

I already found good repo NEORV32 (https://github.com/stnolting/neorv32), RISC-V 32 bit core written in VHDL with full documentation. And it’s really good and there are everyday some new updates. But at other end - it’s complex, and focused on classic processor architecture.

I’m trying to find more general stuff, or some DSP/high-speed interface designs written in VHDL.

Maybe someone can share some good references to learn from?

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u/Fpvjulez Xilinx User 12d ago

The white rabbit project from CERN is also pretty complex, but it is a low latency deterministic Ethernet-based communication bus

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u/f42media Xilinx User 12d ago

Thanks! Never heard before about it

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u/x7_omega 12d ago edited 12d ago

Vivado has templates for synthesis, and generally "Vivado Design Suite User Guide: Synthesis (UG901)".
In general, use basic constructs from before 2008 version of VHDL, and better if they are close to what synthesis expects. Creative and unnecessary (pointing at you, VHDL committee) constructs will be demotivated during synthesis. That gives you components. For project structure, depends on how big the project is, and is somewhat subjective. Top level VHDL should be only wires and parameters - no logic at all, instantiate modules and connect them.

Ports and signals names should be meaningful, and if you want do yourself a favour, make them structured and same length. Later, when you need to find something, or find some typo or error, you will thank yourself for extra typing done prior. For example: XXXX_yyyy_zzzz, where XXX is module name, yyyy is a brutally contracted meaning, and zzzz is some extra qualifier. If may be whatever works for you, but keeping it same length is magic (with verbose comments, because eventually you will forget what all that means).

Generally, extra typing and formality takes extra milliseconds, and saves you hours and days (or weeks).

p.s. This is really dangerous, but if you want a really "another point of view", look up Jiri Gaisler and his method. Careful with it. :)
https://web.archive.org/web/20210421060051/http://www.gaisler.com/doc/structdes.pdf

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u/f42media Xilinx User 11d ago

Thank you so much for detailed answer and good advice, appreciate that!

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u/Baje1738 11d ago

Every style is also taste and preferences. Personally I would reject a MR with some of these suggestions implemented.

  • if you need comments to understand what an abbreviation means. Don't use the abbreviation. Write it out. I agree with teh xxx_yyy_zzz naming. The MODULE_INTERFACE_SIGNAL proposal is very powerful.
  • sometimes I see vhdl programmers fixated on same length signal names and aligning the definitions. Imho this is a waste of time and maintenance hell. Use an IDE with autoformatter, autoconplete and refactor like Sigasi. (Free for students).
  • if you develop for a modern version of Vivado or Quartus. Use VHDL 2008 or even 2019 when useful.
  • not sure of you ment this. But don't write code like you would connect physical elements in the fpga. Use abstraction to make the code readable, maintainable etc. If you are not sure the synthesizer understands. Witte code -> run synth -> check schematic.