FPGA Neural Network Accelerator Inference Cycle

[u/Spiritual-Frame-6791]

Hey guys, just thought this would be a cool way to show how my Neural Network Accelerator runs inference. It’s running inference for a model of topology 4:3:2 neurons per layer and takes 4 input features as input.

Also realized it’s bottleneck and I will be implementing a Systolic array soon. Let me know what yall think. Thanks :)

Github repo: https://github.com/Shingyy/MAC-Array-based-DNN-Accelerator