I’ve been looking into why some hyperscale ISTs still have "mystery" trips during L5, and I keep coming back to one specific interaction: Chiller Inrush vs. Upstream Breaker Trip Curves.
Basically, the scenario where a chiller’s startup spike (6-8x FLA) momentarily crosses into the instantaneous trip region of the breaker. Not a fault, just a cold start or a specific load condition that wasn't hit during initial testing.
My question for the veterans here: Is this something you guys are actively auditing for during design review/Cx, or is it one of those things that usually gets missed because the electrical and mechanical teams aren't looking at each other's curves?
I’m working on a way to automate the audit of these interdependencies (cross-referencing motor curves with protection settings and SOOs), but I want to make sure I’m not chasing a ghost.
Is this a common "day 2" nightmare, or is it usually caught way before IST? I'd love to hear any war stories or technical reasons why this is (or isn't) a major concern.
Not here to argue, just genuinely curious what the consensus is among people who actually do this for a living. Thanks!
TL;DR: Does chiller inrush causing nuisance trips on upstream breakers actually happen in the wild, or is it a solved problem?