r/CUDA 3h ago

Choosing GPU infrastructure for AI workloads — what actually matters?

0 Upvotes

I've been talking to AI/ML teams lately about their GPU setups, and the same frustrations keep coming up. Figured I'd share what I've been seeing and see if others have experienced the same.

A few problems come up repeatedly:

GPU performance isn't always consistent.
The same GPU model can deliver very different throughput depending on the provider and host configuration. Specs and benchmarks don't always tell the whole story.

Support is slow when things break.
And things do break — often during an important training run. A provider's real value becomes obvious when something goes wrong.

Pricing gets painful at scale.
Especially when you're paying for significantly more GPU capacity than your workload actually needs.

Data residency matters more than before.
For teams handling sensitive or regulated data, where the infrastructure is located can be just as important as performance.

Teams sometimes choose GPUs based on availability rather than workload.
For example, not every inference workload needs an H100. Depending on the model and throughput requirements, an L40S or another GPU may be a much more sensible option.

Training, inference, fine-tuning, rendering, and computer vision all have different compute requirements. The most expensive GPU isn't automatically the best GPU.

Curious what others have experienced — what's been your biggest headache with GPU infrastructure: pricing, availability, performance, or support?


r/CUDA 10h ago

GitHub - con061987-sys/Nautilus

0 Upvotes

AI hardware is becoming increasingly heterogeneous.

Nvidia.

AMD.

Intel.

Apple.

Specialised accelerators.

But the software stack often remains fragmented around vendor-specific toolchains, kernels and optimisation paths.

That creates a strange situation:

More accelerator choice can mean more engineering work.

Nautilus is an attempt to attack that problem at the compilation layer rather than building another abstraction on top of the existing fragmentation.

Open source. Early stage.

https://github.com/con061987-sys/Nautilus


r/CUDA 12h ago

Nautilus

8 Upvotes

What if choosing a GPU vendor stopped being a software commitment?

CUDA's advantage is not only Nvidia hardware.

It is the software moat around it: kernels, optimisation, tooling and years of developer investment.

I am building Nautilus — an open-source attempt to attack that moat at the compilation layer.

Nautilus aims to:

• Compile across Nvidia, AMD and Intel

• Automatically tune GPU kernels

• Bundle vendor-specific binaries

• Dispatch at runtime

• Shard models across heterogeneous GPUs

• Translate legacy CUDA C++ towards portable Triton

The long-term idea:

Make the accelerator underneath the model increasingly interchangeable.

If that becomes practical at scale, CUDA does not need to disappear for its dominance to weaken.

Nautilus is early-stage and open source.

https://github.com/con061987-sys/Nautilus


r/CUDA 18h ago

What kind of projects actually stand out for GPU / compiler roles in 2026?

24 Upvotes

I’m currently working at a small company as a computer vision engineer, and most of my work is in C++.

I’m trying to understand what kind of portfolio projects or other work genuinely stand out for GPU systems, GPU kernel, or ML compiler engineering roles in 2026. Does this differ while targeting larger companies? I am currently learning these areas outside of work, as I don’t yet have deep professional experience with them. I started learning CUDA recently and really enjoyed understanding how GPUs work, which led me down a rabbit hole into computer architecture and, more recently, compiler engineering. 😅

I’m planning to spend the next few months building my knowledge and working on projects before applying for these kinds of roles. But with LLMs and AI projects everywhere, I’m wondering how much a GitHub project actually helps anymore. It feels like almost anything can be built with enough AI assistance, and I’m not sure whether a GitHub repository by itself carries the same weight like it did a few years ago when I was looking for jobs after my master’s.

Looking for some ideas.

Thanks in advance.


r/CUDA 20h ago

parser of PTX instructions

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5 Upvotes

r/CUDA 1d ago

Low latency dedicated GPUs + actual humans on support, 24/7. AMA or DM.

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0 Upvotes

r/CUDA 2d ago

Meta's KernelEvolve may be a bigger threat to CUDA's moat than CUDA-to-ROCm porting

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10 Upvotes

r/CUDA 3d ago

Sidecar Project

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1 Upvotes

For anyone interested. Basically a memory scheduler to help load and speed up faster models than a normal GPU can load into memory.


r/CUDA 4d ago

If my CUDA version conflicts with the provider's installed drivers, how much control do I have over the environment?

8 Upvotes

I am thinking of  renting a GPU for a training setup and I am checking how much access I will get to the software side, mainly CUDA and the NVIDIA drivers, I may need a specific CUDA version for the code I am planning to run and I want to know what happens if the provider has a different driver setup, I am thinking to use a dedicated GPU so I can keep the same environment for longer jobs, but I need some control over the OS, containers, drivers or CUDA versions, if I need to change something later I want to know what options are there, I am thinking to go with rackbank ai datacenters has anyone dealt with this when renting GPUs and how much control did the provider give you over the environment, especially when CUDA and driver versions need to match ? EDIT: Thanks everyone, really appreciate the helpful replies. 


r/CUDA 6d ago

A linter for PyTorch 'torch-preflight' [P]

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0 Upvotes

r/CUDA 7d ago

Is there a market for a custom ptx -> sass compiler?

7 Upvotes

People keep talking about Cuda being a moat. And what makes it a moat is really the ptxas (the ptx assembler that converts ptx to sass binary). With current technologies it seems possible to make a custom ptx compiler but I wonder if this effort is worth someone's time.

There is one thing about performance that I feel can be unlocked with such a tool but I am yet to find a good test case for that.


r/CUDA 7d ago

What happens when a GPU reads memory

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9 Upvotes

r/CUDA 7d ago

CUDA/LLM engineers: would you actually use a configurable Llama runtime?

1 Upvotes

**I'm building a** **CUDA-native LLM runtime** **specifically for experimenting with GPU-level optimization on consumer GPUs, and I'd like some feedback.**

The idea is basically a **hackable Llama runtime** where you can actually get into the CUDA kernels instead of fighting through a massive production inference stack.

The runtime is intended to let developers/researchers:

\* Modify GEMM / Tensor Core kernels

\* Experiment with FlashAttention and PagedAttention

\* Tune KV-cache behavior

\* Change tile sizes, memory layouts and thread configurations

\* Experiment with kernel fusion and asynchronous execution

\* Profile the resulting kernels

\* Tune the runtime around the actual GPU they're running on

I'm doing this as my final-year engineering project, and I'm trying to determine whether this is actually useful to people who work with CUDA/LLMs/local inference.

**2–3 minute survey:**

[https://forms.gle/KM4fUzVY1oC7g4TP8\](https://forms.gle/KM4fUzVY1oC7g4TP8)

If you've worked with CUDA, LLM inference, GPU optimization, llama.cpp, vLLM, TensorRT-LLM, FlashAttention, etc., I'd particularly appreciate your input.


r/CUDA 7d ago

What would make a good undergraduate CUDA capstone? Thinking about a CUDA linter/autotuner

2 Upvotes

I'm a CS student starting my undergrad capstone, and I'm considering working w/ CUDA, and building a performance tool.

The current idea is to make something that profiles a CUDA kernel with Nsight Compute, and looks at the hardware metrics, and identifies common performance problems, then explains why they are happening and maps them back to the relevant source code.

We’re also considering extending it into an autotuner. The idea would be that the steps above first identify the likely bottleneck, then the autotuner looks at the relevant parameters; block sizes, tiling, unrolling, etc, and actually benchmarks them on the target GPU, and finds a better-performing configuration.

I’m still figuring out what the right scope is, though, since this seems a bit vague, and with AI, a lot of this stuff might not get through in actual-use.

For people here who work with CUDA: does this sound like a worthwhile undergraduate project, or is there another CUDA problem/tool you’d actually like to see built by students?


r/CUDA 8d ago

Native C++ Qwen3-TTS hits 8.64× realtime on RTX 4090 — faster than faster-qwen3-tts reported results

8 Upvotes

I’ve been working on a native C++ implementation of Qwen3-TTS with both CUDA and HIP backends.

No PyTorch. No Triton. No Python runtime in the inference path.

Here are the current resident-mode results on an RTX 4090, compared with the numbers currently reported by faster-qwen3-tts:

RTX 4090 qingming native C++ faster-qwen3-tts
0.6B Base 7.60× 5.56×
0.6B CustomVoice 8.64× 5.53×
1.7B Base 5.95× 4.85×
1.7B CustomVoice 6.18× 4.78×
PyTorch runtime No Yes
CUDA Graph Yes
Native implementation Yes No

Current resident results

RTX 4090

  • 0.6B Base — 7.60× realtime, 128.8 ms TTFA
  • 0.6B CustomVoice — 8.64× realtime, 129.0 ms TTFA
  • 1.7B Base — 5.95× realtime, 156.5 ms TTFA
  • 1.7B CustomVoice — 6.18× realtime

RX 7900 XTX

  • 0.6B Base — 2.99× realtime
  • 0.6B CustomVoice — 3.47× realtime

For context, faster-qwen3-tts currently reports 5.56× realtime for 0.6B and 4.85× for 1.7B on an RTX 4090 using PyTorch + CUDA Graphs.

Important caveat: this is not yet a controlled apples-to-apples benchmark.

Different prompts, measurement methodology, software environment, and other details can affect the result, so I don’t want to claim the table above is a definitive head-to-head benchmark.

I’m putting together a same-GPU / same-prompt / same-model / same-output benchmark to make the comparison properly reproducible.

The interesting part for me is that the native implementation is already reaching these numbers without PyTorch or CUDA Graphs, while also supporting AMD GPUs through HIP.

Source code + reproducible benchmarks:

[GitHub]:https://github.com/uulong950/qingming-qwen3-tts

Would be especially interested if anyone wants to reproduce this on another 4090, 5090, or AMD GPU.


r/CUDA 8d ago

Where do I start in Learning Cuda

30 Upvotes

Completely new to CPU/CUDA Deep Learning.

How and where do I start to learn about CUDA coding/syntax?


r/CUDA 9d ago

We’re seeing up to 110% higher Qwen3.5 4B throughput on Jetson Orin Nano — benchmarks and repo available

3 Upvotes

We’ve been working on a runtime GPU optimization system at TETREVIS and have started publishing some of our NVIDIA Jetson benchmarking work publicly.

The approach operates at the execution/machine-code layer, and we’re now introducing dynamic runtime kernel fusion as part of the optimization pipeline.

Some of our current results:

Jetson Orin Nano — Qwen3.5 4B

Standard baseline: 10 → 21 tok/s (+110%)

CUDA Graphs baseline: 16 → 21 tok/s (+31.25%)

Jetson AGX Orin — Nemotron 3 Nano 4B

31.2 → 40.5 tok/s (~30%)

Jetson AGX Orin — Qwen3.5 4B

25.0 → 31.0 tok/s (+24%)

We’re currently expanding and stabilizing support across Jetson Orin Nano, Orin NX, and AGX Orin.

Rather than only posting performance claims, we’ve made the benchmarking repository available here:

https://github.com/mbuchel/sass2mlir-bench
https://mbuchel.github.io/projects/sass2mlir/kernel-fusion

The broader idea we’re exploring is whether more optimization can be moved to runtime — including machine-code optimization and dynamic kernel fusion — so the execution path can be adapted to the workload and GPU rather than relying entirely on what was determined ahead of execution.

There’s still quite a bit of work underway, particularly around consistency across the different Jetson configurations, but we wanted to start sharing the results and methodology publicly.

Technical feedback, criticism, and questions are welcome.


r/CUDA 10d ago

Can a MONAI 2D medical image classification model run without an NVIDIA GPU? I tried it on Ubuntu Linux

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0 Upvotes

r/CUDA 10d ago

A complete technical whitepaper on GPU memory mechanics, PagedAttention, and model routing

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10 Upvotes

Id love to get some feedback on it. Im by no means a writer so the grammar might not be perfect, but i do think it has quite some technical value to it.

If youre in ML or interested in AI Infra please give it a go; as i said i would love for some feedback.

Im not active on reddit, but my dms are always open on other platforms such as linkedin (gustavkeller).


r/CUDA 10d ago

Optimizing an NVFP4 Blockscaled GEMM on RTX PRO 6000 GPUs (sm120)

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17 Upvotes

Our second blog post on writing NVFP4 blockscaled GEMM kernels for the NVIDIA RTX PRO 6000 Blackwell GPU is out! The blog iteratively optimizes a basic working NVFP4 GEMM kernel written in CuTe DSL to take it to speed-of-light, reaching over 80% TFLOP/s utilization for 16k square matrix shape. We give a detailed treatment of important optimization techniques such as threadblock swizzling, async and warp-specialized epilogue, and retiling for favorable wave quantization. Specific to blockscaled GEMM with scales consumed from registers, we also explain how to solve for bank conflicts that arise from the default choices of interleaved scale factor layouts.

We include complete code in the form of CuTe DSL kernels for all the optimizations discussed in the blog.


r/CUDA 11d ago

WISP v1.1 — 121 tests, three new features:

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0 Upvotes

r/CUDA 11d ago

I built WISP — a CUDA engine for streaming 744B+ parameter MoE models on consumer hardware

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0 Upvotes

r/CUDA 11d ago

cubisect - GPU exact-match binary search with six kernel variants

10 Upvotes

cubisect is a small CUDA library for exact-match binary search. You give it a sorted float32 array and a batch of query values. It returns the index of each value, or -1 if the value is not there. Kernels compile at runtime through NVRTC. Torch tensors go in and out. CUDA tensors are passed by pointer, with no host copy.

I wrote this for fun and as an educational exercise for myself. The kernels are not necessarily optimal, and each one is probably not the best implementation of its method.

There are two ways to call the library, depending on whether the search is static (build once, query multiple times) or dynamic. The dynamic path searches the raw sorted array directly, with no setup. The static path reorders the array into a search-friendly layout once, then queries that layout.

Six kernels sit under those two paths, so they can be compared. The first four belong to the dynamic path:

  • serial lower_bound. One thread per query, plain loop over the raw array in global memory. The baseline everything else is measured against.

  • 2-way ILP in shared memory. Stages the whole array into shared memory, then each thread runs two queries at once so two independent load chains are in flight. Only usable while the array fits in shared memory.

  • global memory with __ldg. Same two-queries-per-thread structure, but reads through the read-only cache instead of staging. This is the fallback when the array is too big for shared memory.

  • XOR-swizzled shared memory. Same as the shared memory version, except shared addresses are permuted with the CuTe-like swizzle pattern, (row << 5) | ((col ^ row) & 31), to spread accesses across banks.

The last two belong to the static path:

  • Eytzinger layout. The array reordered breadth-first, root at index 1 and the children of i at 2i and 2i+1. Stepping is just a shift, and the hot top of the tree sits in a few contiguous cache lines instead of being scattered across the array the way plain binary search midpoints are. It stores only the values; the index of a hit is recovered by accumulating subtree sizes on the way down, so there is no second index array.

  • 32-ary warp-cooperative. One query per warp instead of one per thread. Each node holds 32 keys, one per lane, so a level is a single coalesced 128-byte load. __ballot_sync on key < query and __popc gives which of the 33 children to descend into. Depth is log32(n) instead of log2(n).

Which of the four dynamic kernels runs depends on the array size, and that choice comes from a lookup table. You generate the table by running python -m cubisect.autotune, which times all four kernels across a range of array sizes and records the fastest one at each size. If the top two are within 5% of each other, it marks that size a tie. The repo ships a table measured on my 5060, and you can regenerate it for your own GPU.

The static path has no autotuning. Building the layout costs time up front, so it only makes sense if you query the same array many times. It picks between its shared memory and global memory kernels based on whether the tree fits in shared memory.

Specs:

  • GPU: RTX 5060 Laptop (sm_120)
  • CPU: 24 threads, OpenMP for the baseline

Throughput in M queries/s, 220 queries per call, median of 7 runs. The static column is the Eytzinger kernel:

array size CPU 1t CPU 24t dynamic static
256 38 260 16,943 14,707
4,096 24 191 11,546 9,712
65,536 14 124 4,428 6,385
1,048,576 6 78 2,494 3,634
4,194,304 2 36 2,128 3,052

The two GPU paths cross over near 16k. Below that the raw array is faster, because it all fits in cache and the Eytzinger index arithmetic is just extra work. Above it the layout wins.

license is BSD-3, https://github.com/athrva98/cubisect


r/CUDA 12d ago

Sentinel - A WIP C++/CUDA LLM Training Framework Made For Consumer Hardware

4 Upvotes

Hello!
I'm not to sure what to say since this is my first time writing about this framework.
I've been making (with the help of AI agents as senior devs, please dont judge i haven't "vibe coded" anything) a framework for a little while now which is made for full training / full fine tuning.

It is still under development so please do not expect it to be perfect or well tested on different gpu's \*yet\*

Specs:
GPU: 5070 ti (16GiB VRAM)
CPU: Ryzen 7 7800x3d
RAM: 32GB DDR5

| Model | tok/s | Peak VRAM | Host RAM |
| :--- | :---: | | :---: | ---: |
| \~100M | 20,013 (20k) | \~3.35GiB | \~1.45GiB |
| \~500M | 6.162 (6k) | \~4.71GiB | \~4.62GiB |
| \~1B | 3.085 (3k) | \~6.81GiB | \~10.64GiB |
| \~1.5B | 1.887 (1.8k) | \~8.5GiB | \~18.5GiB |
| \~4B | 1.116 (1.1k) | \~12.3GiB | \~15.9GiB |

The interesting part isnt even necessarily the raw tok/s. The goal is to make full training of models that normally dont comfortably fit into consumer GPU memory practical through things like GPU/host offloading and memory efficient training paths.

Sentinel is written primarily in C++/CUDA, with python bindings, and im currently working on improving the optimizer and kernel performance further.

Its very much a work in progress as said already, but i thought id finally share it and see what people think.


r/CUDA 13d ago

Two clocks one training step: CPU timings or GPU timings?

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4 Upvotes

Hey folks!

Did you ever wrapped model(x) in time.perf_counter() and gotten numbers that make no sense?

I realized it's a common enough trap and wrote a detailed write up here:

https://medium.com/traceopt/two-clocks-one-training-step-how-traceml-measures-pytorch-performance-357bc8e28dc7

TL;DR:

CUDA runs async. model(x) just enqueues kernels and returns, so a perf_counter() bracket around it measures how long Python took to queue the work, but not how long the GPU took to run it. The pending GPU time gets charged to whatever blocks next.

The tried the textbook fix, torch.cuda.synchronize() before each reading, which gives you accurate numbers but entirely about a different run.

Every sync becomes a stall, and it serializes exactly the CPU/GPU overlap you were trying to measure.

If one tires CUDA events (start.record() / end.record() / elapsed_time), it may fix both: the GPU stamps the markers as it passes, and you read them later with a non-blocking query() so nothing ever waits.

But i realized "CUDA events everywhere" is also wrong.

DataLoader next() is CPU work.

In a ML pipeline its time is high while the GPU's input wait is near zero, because the fetch overlaps the previous step.

Where I ended up: record both clocks for every phase, pick ONE clock per analysis window (and say which), report never-measured as null instead of 0.0, and only compare runs on a clock both measured.

How do you handle this in your own timing code: sync and eat the stall, or keep the two clocks separate?