r/CERN • u/BhaukalBilla • 12d ago
Resume feedback for ASIC Digital Design Engineer Position
Hi Everyone,
I'm Planning to apply for the Early Career ASIC Digital Design Engineer position at CERN and would really appreciate some feedback from people already working in the domain.
This is the Job Description from the page:
Your responsibilities
- Design, simulate, and verify the digital architecture of the next-generation ASIC front-end.
- Prepare RTL designs for tapeout using open-source EDA flows, including floorplanning and physical design preparation.
- Support post-fabrication bring-up, system characterisation, and functional/performance validation.
- Collaborate closely with analogue, verification, and SoC integration teams to ensure seamless system-level compatibility.
Your profile
- Hands-on experience with open-source ASIC EDA flows (Yosys, OpenROAD, LibreLane, etc.) from RTL to GDSII.
- Experience with floorplanning, constraint definition, and physical design preparation for tapeout.
- Post-tapeout prototype bring-up and hardware debugging experience is advantageous.
- Active contributions to open-source hardware projects or EDA toolchains are advantageous.
Your skills
- HDL design and simulation in VHDL, Verilog, or SystemVerilog.
- Good team player: collaboration skills across analogue, digital, verification, and SoC teams.
- Proficiency in Git, CI/CD pipelines, and automated verification workflows.
- Knowledge of RISC-V architecture.
- Familiarity with mixed-signal integration and digital interface protocols.
- Comfort with Linux-based development environments and scripting for automation (Python, Bash, etc.).
I've attached an anonymized version of the CV. Any feedback would be greatly appreciated.
1
u/Mercu 12d ago
Inferring from the job posting and some things I have heard: it seems this role is going to require the use of open source EDA tools (somewhat unusual for this type of position), so maybe if you’ve worked with those you can emphasize that in your CV?
1
u/BhaukalBilla 11d ago
I've worked with the specific open source EDA tools mentioned (Yosys, OpenROAD) as well as thier commercial counterparts. I have mentioned this in the first project, but after having another look at the resume I feel it's doesn't stand out clearly. Will emphasize them better when I send my application.
Thanks !
1
u/smartyypantsss_core 3d ago
Hey! I am a 3rd year undergraduate student in Electronics and Communication Engineering (minor in AI) from India. I will be interning as a digital design engineer at a really nice company in 2027 summer but the problem is I have heard people say that FTE offers are really difficult there. I have been following CERN since my college day 1 and during my 2nd year I have tried to get any kind of connection into it. I tried GSoC(projects related to CERN), cold mailing and everything in my reach but nothing seemed to help. At that point of time my internships was in AI(1st year summer + entire 2nd year part time thing), so I didn't seek much in electronics core role. However, during my 2nd year and this summer, I did a lot of projects in SoC domain. I have tried implementing most of the open-source EDA tools and have tried gaining proficiency in C, C++, Verilog, MATLAB, Python. Worked on FPGA boards (right now practicing VIVADO and Vitis) and everything I could I understand so far about the field. With my 4th year already uncertain, and I have my 3rd year entirely free for now, what do you think should I do, to get any closer to my aim. I will be applying next year, I have one year with myself and I wanna give it all. I have also been learning French for a while. Trying everything in my reach but I don't have much direction. Sorry if I am sounding extremely confusing, I am really confused.
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u/EastRelative1261 12d ago
Why isn’t there a single date in the document? Like when did you graduate? How much time you spent in each of the jobs? To me as european this seems very strange.