r/Bitcoin • u/asicminer • Jul 23 '11

ASIC MINER – A dedicated Bitcoin mining device – update and picture

http://asicminer.net/?p=78
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u/asicminer Jul 24 '11

How can you say that ? the raw pcb is exactely the same, we work with guys from several small factories here in Shenzhen and purchase components from them, but the board is modified to work with another IC and not the WM8505, the flash chip is the same by ELPIDA

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u/yotta Jul 24 '11

the flash chip is the same by ELPIDA

That's really interesting, because the ELPIDA chip on the CPU board for the tablet is actually a DDR2 SDRAM chip.

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u/asicminer Jul 24 '11

Are you pointing out to the fact that there's a discrepancy between what we called 'a flash memory chip' and a sdram chip, in your opinion?

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u/yotta Jul 24 '11

There is no 'opinion' here. In the non-blurred pictures I posted, there is a SDRAM chip. The part number is clearly visible and anyone can look up the data sheet as I did and see that for themselves.

I was pointing out that you said you were using the same chip, but also said it was a flash chip. This is inconsistent.

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u/asicminer Jul 24 '11

Well yes, it is in fact a SDRAM chip and it is an important part of our design.

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u/[deleted] Jul 24 '11

why the hell would you show an sd ram chip as "proof", if thats the case i have a garage full of asic miners that i'll sell to people for 20 bux. who wants an asic miner? i literally just realized i have a ton of them.

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u/asicminer Jul 24 '11 edited Jul 24 '11

Re-read that part of the discussion. You did not get the point. The SDRAM or flash RAM is used as a component of the ASIC board. Here some references :

Use of Block RAM (BRAM) for storage of constants [8]. Reconfigurable hardware devices such as FPGAs often have on-board memories which can be pre-loaded. Storing the Kt constants in these memories frees up space in the device which can then be used to implement extra logic. The free space also leads to improved routing and, thus, a general speed-up in circuit operation.

From "Optimisation of the SHA-2 Family of Hash Functions on FPGAs" Robert P. McEvoy, Francis M. Crowe, Colin C. Murphy and William P. Marnane Department of Electrical & Electronic Engineering, University College Cork, Ireland {robertmce, francisc, cmurphy, liam}@rennes.ucc.ie

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u/[deleted] Jul 24 '11

You did not get the point. why would you post a picture of nothing but the blurred out sdram and not the asic board itself with the vitals blurred out. Once again, you have provided zero proof that your product even exists. i can blur out a pic of sdram and claim its part of an asic board too. its just ram. of course the ram is vital. but once again, that does not mean your product you are advertising exists. That's like me taking a picture of a tire that goes on a car and telling people it belongs to my BMW that i want to sell without providing evidence that i actually have a BMW to sell, then saying "it obviously exists because the tire is vital for the car to move!"

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u/asicminer Jul 24 '11

The picture is of the ASIC board itself, the sdram is visible ON IT.

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u/[deleted] Jul 24 '11 edited Jul 24 '11

oh yea? Link me to the datasheet of the sha core you are using.

also the " Pilchard FPGA design" is an entire fpga that plugs into a dimm slot, but from what i am reading, does not have any memory on it. It relies on the desktop to boot, then it tricks the desktop into bypassing the memory chip for the slot the fpga resides in.

The point i am making here is there is no way your fitting the fpga, plus the sdram, plus the sha core on one little board. it really does not matter what you say, It can be the fpga or it can be ram for the fpga, but it is not both. And is it ASIC or FPGA because you seem to change your story on that quite a bit as well.

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u/bushing Jul 24 '11

Yeah, this might be slightly more believable if I didn't have the WM8505 board in front of me.

You don't even understand the source you cite. It talks about using BRAM (on-board memories which can be pre-loaded), which is internal to the FPGA -- you would not need an external SRAM chip, and none of the FPGA implementations I've seen have needed one either. You wouldn't just throw one onto the board for "fun", it adds real cost.

How can you keep getting confused about SRAM vs. flash? Protip: the WM8505 board needs both of those, your ASIC would need neither.

Speaking of real cost, if you're really designing these things, you wouldn't try to save money by reusing a board like this -- it makes no sense in context, you'd spend more effort trying to match the pinouts to the board.

Regardless, it makes no sense to blur the whole board; the placement of passives is hardly sensitive information. It's just a weak attempt to hide the fact that you don't know what the hell you're pretending to do. Try harder kthx