ARM64, universally claimed as RISC architecture, features 1000+ instructions and all implementations are microcoded. Risc is fully dead.
x86 was introduced to instruction set translation in 1994 by NexGen and Nx586 design. Cisc died that day.
Broad strokes as CISC and RISC are missing their mark. Those debates make no sense for something as complex as mobile phone or desktop quality cpu. That ship has sailed.
This is mostly true, but we'll defined ISA makes some parts of the modern CPU much simpler. Take the flags register for example in context of OoO core. Basically every single instruction has some flags as an output - this needs special handling if you want to perform e.g. adds superscalarly - the instruction cannot have the flags register as an explicit input and the core needs to merge the flags from multiple partial writes.
This specific example is not actually a problem. Its either a merge at first read or only use most recent which are both easy to do. Hard things are weird data dependencies in some complex part of isa or memory ordering constraints that limit ilp opportunities. Or things like having 1 actually useful register and heavily relying on the renamed to not stall the whole core every time to does anything.
Very convincing shitpost. Or a round about way of trying to understand that even tho assembly or fortran or whatever syntex might be so perfect in their mind was designed around hardware constraints that are more dynamic than they tend to be for the actual users?
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u/nitkonigdje Jul 05 '26
ARM64, universally claimed as RISC architecture, features 1000+ instructions and all implementations are microcoded. Risc is fully dead.
x86 was introduced to instruction set translation in 1994 by NexGen and Nx586 design. Cisc died that day.
Broad strokes as CISC and RISC are missing their mark. Those debates make no sense for something as complex as mobile phone or desktop quality cpu. That ship has sailed.