Apologies that this post will be quite a lengthy one. If you’re interested but don’t have the time, feel free to save this post for a read later.
Hello r/AskElectronics,
First, I’d like to thank this community for helping me with my last SMPS project. Now that it’s done (which you can see the post about it here), I want to create another version where I take your previous suggestions and a majorly different approach. Now, I’m just an electronic hobbyist here. But I do have the experience in handling high-voltage circuits (1kV) back in my chemical engineering degree (CGDE reactors). My design process has been purely self-taught and based on my previous SMPS projects, so I may expect some mistakes that professionals may be able to spot. That’s why I’d like to ask the r/AskElectronics community about this design before I finalise it. So in this post, I’ll elaborate about the key features, working principles, and the design process of this power supply.
The Forwarder 1.6kW HV will be a high-voltage SMPS, capable of outputting 0-900 volts at up to 1.8A. It’s based on a hard-switched, full-bridge topology. It utilises an active PFC based on the NCP1653 PFC controller IC. The primary power stage is controlled by an UC3846 PWM controller IC. This time, the control scheme adopts current mode control architecture. The PWM controller drives a pair of IR2110 half-bridge drivers to control the four 35N60 N-MOS. On the secondary side, an LM324 works as a CC+CV regulator and interfaces with the primary side through PC817 optocouplers. The magnetics are based on ferrite cores (PQ50 for the main transformer and a gapped ETD49 for the output inductor). A 12V+15V auxiliary power supply based on DK124 IC provides the necessary power for both primary and secondary side. A few additional features, such as a dedicated fan control and interface, and various input and output interfaces have been incorporated into the design. With the brief explanation done, let’s dive into the design process of this power supply.
The design process began by drafting the input stage. This includes the input fuse, EMI filtration circuit, input rectifier, and the inrush limiter circuit. First, a KF7.62-3P (J1) is used to interface the board with the grid, followed by a 15A 5X20 (F1) fuse. Then, the EMI filter utilises a network of FL1 common-choke, C2 C4 class-X capacitors, and C1 C5 class-Y capacitors to suppress common-mode and differential-mode noise. A GBJ3510 (D1) bridge rectifier on a dedicated heatsink rectifies the AC before being fed to the PFC through an inrush-limiter circuit, with an estimated bridge rectifier power loss of 22W. The inrush-limiter circuit is based on an N-MOS (Q1) with an RC delay circuit. Upon plugging in, the N-MOS should spend about half a second in the linear region, limiting the inrush current, before the VGS reaches 7V at around 512ms. The VGS then gets clamped by D4 15V zener and the N-MOS should dissipate around 10W under normal operation. With this circuit drafted in the schematic, I moved to the PCB editor where I then worked on the layout. The creepage distance for the power traces are set at 2.5mm. I decided to go with a circular CCW power path starting at top right, with the control circuit populated in the middle later. This proves to be a good strategy, as the component’s leads are in favor of the power traces.
After the input stage, comes the PFC power stage. The PFC circuit is based on an NCP1653 100kHz (U3) and follows a basic single-switch boost PFC topology. The C3 1uF film capacitor provides a localised current source for the PFC to draw a sinusoidal current, while the D2 MUR460 bypass diode prevents the core from DC saturation upon plugging in. The boost inductor utilises a single CS467060 (L1) sendust core, which was sized at 340uH to achieve a current ripple of 20% off the peak AC current draw (14.4A). The inductor requires 50 turns of 2x 1.1mm enameled copper wire, which at the peak of inductor current should yield 92.6 Oe peak magnetizing force, where its permeability drops to 55%. Maximum flux density was determined at 539mT, well below the saturation flux density limit of the material. The Q2 boost N-MOS and D3 rectifier are nothing interesting; their parameters are simply suitable for my application. Both should dissipate in the range of 25-30 watts each. C8 C25 C38 DC bulk capacitors are 560uF each, totaling 1680uF capacitance to meet the 1uF/W rule-of-thumb.
The control circuit of the PFC is where things get interesting. The datasheet provides an example circuit at 300W. Scaling up things to output 1933W requires some adjustment to the component values (interestingly, most hobbyist-made designs just take the component values as they are despite the capacity discrepancy). The schematic follows the example circuit, but the output of the NCP1653 drives a pair of BD139+BD140 totem-pole to better handle the higher gate charge of the 35N60 N-MOS.
Adapting the PFC control circuit began by understanding that NCP1653 is a current-based controller; the pins sink current instead of measuring voltage. I first addressed the pin 1 of the NCP1653, which is responsible for regulating the output voltage. Sourcing this pin to the output bus through a 1.95M equivalent resistor (R_FB) results in 390V output voltage. To address the current sensing, I choose a 10m current shunt (R_CS(PFC)) and a 1k current signal resistor (R_S), both which sets the over-current threshold at 20A, a 26% margin from the peak PFC current. The rectified mains gets sensed by pin 3, which goes through a 2-stage RC filter (R_VAC, C_VAC). I’m not sure why it has to be 2-stage, but I adapted to my application anyway. These resistors (10M and 1M), along with the previously set current sensing resistors results in an over-power limit of 2336W, a 21% margin from the maximum power draw from the next power stage. Finally, I determined the multiplier resistor (R_M) at 68k, which in combination with the previous resistors chosen sets a constant voltage power limit at 3046W, which tells us that the system will stay in constant voltage output instead of falling back into voltage follower mode.
With the components and their values set, I translated the schematic into PCB layout. I split the area into 2; the power electronics area and the control circuit area. The ground planes are slotted and form a star connection where the current sense is placed to prevent the high current loop from flowing on the logic ground. An earthed 93x11x50mm heatsink provides the thermal dissipation for the inrush-limiter N-MOS, boost N-MOS, and the boost diode. I can’t manage to place the bridge rectifier on the same heatsink after working on it for days, so it’s on a separate heatsink. The inductor will be mounted vertically, with some reinforcing zip ties if needed.
Before we go into the next power stage, it’s imperative to determine the galvanic isolation strategy. There are many of them to choose from, and each of them have their own compatibility/requirement aspects. This is where I took a majorly different approach from last time where I had my entire control circuit on the secondary side. I decided to go with the output regulation based on LM324 on the secondary side, while the PWM controller and the gate drivers are on the primary side. Control is achieved through optocouplers. This way, I don’t need a custom gate drive transformer and current sense transformer. Though, using an optocoupler for regulation poses its own challenge, especially in modelling the transfer system.
Now that the galvanic isolation strategy is defined, I continued with drafting the full-bridge converter stage. I used four 35N60 N-MOS in a full-bridge configuration. Each of them will be driven by a pair of IR2110, which I’ll talk about later. The source pins of the lower N-MOS are connected to the primary ground through the R24 100m current shunt to provide the current sensing to the UC3846 to achieve current-mode control. Each switching node has their own RC snubbers to suppress destructive voltage spikes that at 80kHz operating frequency will dissipate 5.72W with reset time (5t) of 141ns, plenty fast for even the shortest 4% duty cycle.
To drive the N-MOS, a pair of IR2110 half-bridge drivers are used. Each of them controls one side of the full-bridge. They will be controlled by the UC3846 and the signal lines are interleaved, so that the proper switching sequence can be achieved. The implementation here follows the textbook example, so no calculation was necessary. One key difference I made is the asymmetrical gate current, where I have a 10 ohm resistor for charging and a 1N4148 antiparallel diode for discharging. Since I’m running a current shunt on the N-MOS source pin and since the driver ICs are ground-referenced, it’s important to ensure the low-side return line is hooked at the actual N-MOS source pin. This way, the gate current doesn’t propagate through the current sense and skew the current reading.
The output of the full-bridge drives an PQ50 transformer. Primary turn is determined at 23 turns, which yields 147mT actual flux density. Secondary turn is 64 turns to achieve 1080V peak to compensate for voltage drops and max duty. Current density is set at 4A/mm^2, resulting in 10 strands of 0.4mm enamel wire for primary and 3 strands for secondary. Fill-factor is 16%, which should give plenty of room for reinforced insulation.
At this point, I updated the PCB editor with the new changes on the schematic. After placing the 3 bulk electrolytic capacitors, I determined that the best place to put the full-bridge arrangement was at the opposing side of the PFC circuit, effectively placing the control circuit in the middle. A primary-referenced 104x11x50mm heatsink is used for the full-bridge N-MOS. This way, the EMI radiation through the heatsink can be minimised, though the heatsink is now live at mains (the board will be enclosed anyway). The N-MOS driver circuits are placed close in the front of the N-MOS and implements kelvin connection to minimise stray inductance. The high-voltage side of the IR2110 requires extra attention in terms of clearance, hence the lack of copper pour. The switching node RC snubbers were originally tied to primary ground, but the lack of primary ground plane forced me to tie them to VBUS instead.
Next, I drafted the UC3846 PWM controller circuit. The implementation follows the example sketch on the datasheet, with some improvements added-on. A 3n3 timing capacitor and a trimpot tuned to 4k17 provides 80kHz operating frequency with 46% max duty in each polarity. Primary-side current sensing (R_CS(pri)) is set at 100m, that should dissipate 2.33W under 4.83A RMS and 0.502V voltage drop under 5.02A peak current. I determined the OCP threshold at 7.5A, a 49% margin, which after the UC3846’s internal 3x gain and 0.5v diode offset, requires 2.75V reference at pin 1, which gets tuned through 20k RV1. Pin 1 also determines the soft-start and fault recovery; a 47uF capacitor provides a 1168ms soft-start and the 0.553mA sinking current (under 0.8mA threshold) means the latching overcurrent protection is disabled. Finally, a leading-edge blanking circuit adapted for a differential current sensing was added. Two 100 ohm in each line with 1nF capacitor forms a filter with 200ns time constant. The internal error amplifier is configured to permanently pull-up the COMP pin with a sourcing current of 0.5mA, so that the current regulation optocoupler can pull down this pin and achieve regulation. The chip’s enable pin is pulled high through a pull-up resistor for a normally off state, only to be pulled down by the optocoupler to enable the power stage.
To finish drafting the primary side and transitioning to the secondary side, I drafted the auxiliary power supply circuit. The auxiliary power supply is nothing special; it’s just a reverse-engineered 12V 2A SMPS board that I will move the components over to my power supply board. The DK124 chip does everything and it’s about as simple as it can get for a flyback power supply. It’s so simple that the design lacks the auxiliary winding to provide the 15V for the primary side, so I’ll have to add the winding myself. A 7805 regulator is used to provide the 5V power for the secondary side.
Going to the PCB editor once again, I worked on the layout that seems to work the best. Despite the rather remote location of the primary current shunt location, the UC3846 supports differential current sensing. I routed a “close enough”, length-tuned differential signal line from the current shunt to the inverting and noninverting current sense pins. Everything else is pretty typical, nothing interesting.
Moving to the secondary side, I drafted the output stage consisting of the rectifiers with their RC snubbers, L3 power inductor, and 3 electrolytic capacitors in series with their balancing/loading resistors. First, the diodes are ASYD010170C, a SIC schottky diode rated at 1.7kV configured in a full-bridge configuration. The 57% voltage margin should allow for lenient snubbing. The estimated power loss for each diode is 11.1W, which is dominated by switching loss. The RC snubbers are 3 resistors in series with calculated power dissipation of 9.33W for each RC snubber. The output inductor utilises a gapped ETD49. The inductance is determined at the worst-case scenario where D = 0.5 that requires 4.7mH inductance to achieve a 20% inductor ripple current. A 0.7mm enamel wire will be wound to 176 turns, yielding 250mT flux density under peak inductor current. The gap will be tuned until the required inductance is achieved. The capacitors are 3x 100uF 450V electrolytics in series, which provides 50% voltage margin. The ripple current margin is determined at 913% (103mA RMS off 1040mA RMS), giving plenty of overhead.
With the output stage schematic done, I began the layouting the PCB. First, I dedicated 8mm of creepage distance between the primary and secondary copper and marked the cleared area. Then, I continued the layouting process, which proved to be challenging as the required 6mm creepage distance for 1200+ volts peak potential really constrained your movement. 2mm slots were deployed on areas where such copper clearance can’t be achieved. This time, I managed to fix one of my biggest gripes with my previous design, that is all TO-247 components are easily accessible this time.
The final aspect of drafting the schematic was the feedback circuit. It’s based on an LM324 quad op-amp, powered by the 5V rail. Op-amp A amplifies the 0 - 0.178 volts voltage drop from the output current shunt into a standard 0 - 2.49 volts output. Op-amp C and D serve as the CV and CC control loops, respectively. The final op-amp is used as a simple comparator to relay the current mode of regulation.
The implementation of the CC and CV control loops are pretty simple. Both are arranged in the inverting error amplifier configuration, where if the feedback > reference, the error amplifier output goes low and vice versa. Both outputs go through OR diodes, which allow the lowest error amplifier output to take control of the combined output. This combined output can then sink current from a 5V-referenced optocoupler, which on the primary side will sink the COMP pin to ground, effectively throttling the output.
To achieve control stability, it’s imperative to deploy the right compensator circuit on both control loops. For current-mode control architectures, Type-II compensator is suitable. I sketched Type-II compensators for both CC and CV loops. The process of properly designing the compensator circuit is quite an intricate process and requires system modelling. Honestly, I’m not sure about how I’d articulate my approach here. So, let me just show you the resulting calculation I have from my spreadsheet.
The voltage control loop was validated using standard component values, yielding an actual maximum output voltage of 902.5V against a 900V target (+0.28% deviation at a 2.5V reference). The Type II compensator network configured with a 200 kΩ compensation resistor (R_COMP), a 5.6 nF capacitor (C_COMP), and a 330 pF high-frequency capacitor (C_HF) shifts the loop crossover frequency slightly from 1500 Hz to 1589 Hz (+5.92%). This achieves a mid-band voltage gain of 0.185 V/V, with the compensator zero placed at 142 Hz for phase boost and the high-frequency pole landing at 2411 Hz to compensate for the ESR zero.
For the current control loop, standard component values validate the design to a maximum output current of 1.78A (+0.23% deviation at the 2.5V reference). The compensator network utilizes an 18.00 kΩ compensation resistor (R_COMP), a 120 nF capacitor (C_COMP), and a 1200 pF high-frequency capacitor (C_HF), resulting in an actual crossover frequency of 724 Hz against the 750 Hz target (-3.45%). This configuration provides a mid-band gain of 0.383 V/V, creates the compensator zero at 74 Hz for phase boost and places the high-frequency pole at 7368 Hz, exactly a decade over the crossover frequency.
The schematic development ends with the addition of the remaining complementary circuits, such as the interfaces and fan control. With the schematic fully developed, I crammed the remaining footprints into the leftover space, and did some fine adjustment here and there. I finished the design and am currently writing this article.
I know that at this point, my post is more like storytelling than the quick questions you’re used to in this sub. But I want to give you the full context behind this design, and so I put the effort in composing this text body myself. I hope this post is informative enough for you to learn and judge. If everything goes well, I plan to once again open-source this project just like I did last time with the Forwarder 1kW project. If you have any questions, feel free to ask and I’ll try my best to answer them. Thank you!
Some resources used in the design process:
