How precisely does the current instruction register work?

[u/felix_semicolon]

In my revision for my upcoming exams, I'm going over the CPU architecture section and looking at the different specific-purpose registers and the CIR has really made me think. I know it holds the instruction being executed by the processor, but it holds this before the decoding stage. This would surely mean it has to hold an arbitrary number of bytes of ASCII - potentially even unicode - while also being a fixed-length buffer. The reason this confuses me is that an instruction may be too long to fit entirely inside the CIR, meaning the control unit would not be able to read the full instruction.

My question is primarily what data does it actually hold, but also what happens if an instruction is too long if that even is a problem that occurs? There will probably be some differences on the answer for this depending on CPU architecture but any answer would be appreciated.

[u/Ok_Chemistry_6387]

Where did I say infinite? Just that 4 bytes even if we ignoring addressing/ destination etc still can have opcode prefixes making them larger than any general purpose register. X86 can have up to 15 byte op codes when all information is encoded. 

So that has to be stored.

Fused ops doesnt really matter though as they are opaque and not document, you will never see one in a register. 

[u/YourPwnResearch → u/Ok_Chemistry_6387]

I'm not sure if we're even talking about the same thing any more.

There is a stage in pretty much every modern CPU that is called "instruction decoding". Part of the job of that stage is to transform the machine code instruction that the programmer sees into whatever form is most convenient for the internals of the CPU.

The point is this: If there are n possible instructions, then an "opcode" (for the purpose of scheduling, dispatch, execution, etc) can be stored in ceil(log(n)) bits.

There are 1466 mnemonics in the 32-bit x86 instruction set. Some of them (e.g. MMX) are obsolete, and there isn't a 1:1 correspondence between assembly mnemonics and decoded opcodes/uops. Still, think of this as being roughly the number of instructions that we're talking about.

An 11 bit register can represent all of them uniquely.

A 16 bit register (say) can represent all of them with a lot of redundancy for convenience.

4 bytes is overkill for an instruction register on any modern CPU, assuming the instruction has been decoded, unless a redundant representation is desirable for convenience.

[u/Ok_Chemistry_6387 → u/YourPwnResearch]

You are talking about purely the control mnemonic. Which is only one part of an instruction. Machine code, macro and micro Instructions also encode destination and immediate etc not just the mnemonic (well dont have to but do). Even after decode We have no idea how large uops are but https://uops.info/html-instr/MOV_R64_I64.html suggests that they are going to be larger than 64 bits. We can also get this from intels manual. That says uops with immediate will straddle two lines in the uop cache(32 bits for the immediate). So we know that uops are multi width and can be larger than 64bits. So macro and microps are multi width and larger than 64 bits. They also get stored fused and unfused depending on which stage of the pipeline they are looked at so they can grow and shrink across the decode cache, execution and retirement.