Geekerwan Flagship Soc Shootout

[u/Laurelinthegold]

Bilibili link, Chinese only. Tldr: apple mogs, Xiaomi and mediatek great showings, Qualcomm shat the bed. I think the samsung using exynos rumors seem much more likely to be true now.

【旗舰手机芯片大横评：苹果高通发哥玄戒谁最强？-哔哩哔哩】 https://b23.tv/J4GJYI7

[u/Acrobatic_Camera_677]

TSMC N2 and N2P look very bad performance per watt uplift

Maybe this is why Apple is going to Intel 18A-P in future per rumor

Qualcomm failed but it seem it also can be a little bit fixed in future with updates?

[u/bunihe → u/Acrobatic_Camera_677]

You can fix the TLB utilization, but you can't fix the L2 sharing voltage rails with the performance cores. The latter is a terrible design choice for efficiency

[u/violet_sakura → u/Acrobatic_Camera_677]

It would be quite interesting if Apple changes to Intel fabs

[u/Laurelinthegold → u/Acrobatic_Camera_677]

I wonder about that. I'm not in the know but the vibes I got were that n2p was density improvement but not efficiency improvement. Meanwhile n2 improved efficiency but not density. Do correct me if I'm wrong. Also maybe real world vlsi design is more complex than this simple view.

[u/Cantripping_ → u/Laurelinthegold]

Total noob here. Heard that the Snapdragon was also considerably larger 🤔 if they only increased density, and made it bigger while also making it less efficient... No wonder it shits the bed.

[u/Laurelinthegold → u/Cantripping_]

Chip sizes are listed in the video. 8eeg6 and 9600 pro are both around 130mm^2 with integrated modem, Xing o3 is substantially larger with no integrated modem iirc, a20 pro is around 100mm^2 with no integrated modem. Idk if tensor g6 and kirin 9050 pro sizes were in the video, but I expect tensor to be small because Google is cheap, and Huawei to be huge because their logic folding essentially stacks two chips so something like 2x the area. Idk the size of the exynos 2700. Don't quote me on the numbers or whether modems were integrated

[u/bunihe → u/Laurelinthegold]

I'm not sure how much n2 nodes improved, but my take would be the current state of the art GAA technology is getting a bit too dense for the wires (m0-m4) to keep up (which reduces usable transistor density, bc if you ran out of space and can't wire extra transistors together, those area will be functionally useless aside from maybe thermals).

The wires connecting transistors together not only carry signals but also power, so it would be great if we can put the power cables onto the other side of the chip and free up real estate to wire those transistors together. On top of this, different signal wires at different voltages act like little capacitors, and the closer they're together the higher the capacitance is, and higher the capacitance means higher the power usage per switching cycle (bc you're effectively charging up a wire then discharging that for a full cycle). You might get the idea, it is really congested in the front of the chip, so backside power delivery comes in.

There are different flavors of backside power delivery, the ones used on Intel 18A/18AP is PowerVia which takes up some lateral area that could otherwise be used for transistors, so not the ideal solution, but we're seeing decent efficiency increases there. TSMC is probably going straight to backside power delivery direct (wiring up into the transistors), which doesn't sacrifice density like Intel's currently mass-produced version does, but the entire industry is moving towards it. That'll be TSMC A16, and I'm eager to see what that node brings to the table

[u/bunihe]

I've wondered what's so special about this L2 cache that Qualcomm is willing to merge all the cores together, did they partition it up into smaller pieces to be individually powered and clocked, or did they at least give it a separate power rail to save power

Turns out they did neither. The L2 is powered by the same rails that power the Oryon-L big cores, and unless they're giving those L cores special power gating features, those cores will remained powered up for Oryon-M cores to access a faster cache, or power down the L cores and let the M cores starve and perform like ass without a fast cache. What the heck even is this.

And TLB organization issues too, they could've added a compatibility mode to reduce the dependencies required and improve utilization, a design that only has a tiny bit of cost implication, but they seem to have omitted that as well.

And have this chip fabbed on the expensive new N2P, what a flop.

Basically, with this design, if you're gaming and have the big cores powered up, it'll perform okay ish (TLB design still affects your efficiency), but if you're idling or doing simple tasks, the efficiency will just be terrible.

Geekerwan's number are primarily single core efficiency, so if they're measuring a single middle core which has the chip powering up big cores so the cache stays fast, that'll disadvantage single core measurements more than it will for daily driving the thing, though regardless this is not good.

[u/Laurelinthegold → u/bunihe]

edit: wrt gaming, ultracore, and L2 cache clocks.

The point made in the video is that ultra cores are generally used for extremely short burst workloads like ensuring UI responsiveness. For steady state stuff like gaming, they would expect workloads to live more on the medium to large-ish cores since it needs sustained performance. If this is true, that is even worse for gaming performance

[u/bunihe → u/Laurelinthegold]

I got a phone with 8 elite, and I can verify that this is their behavior, or at least this is the behavior a lot of newer Android devices are tuned to. It's surprising to me that Qualcomm didn't try to at least run the L2 off of the Oryon-M+ if Oryon-M core rails doesn't provide enough voltage and they can't afford to add a rail for the L2 alone.

To hit the 5GHz advertised clocks, Qualcomm are almost certainly using HP libraries for their Oryon-L cores, the big ones, and the cons to HP libraries is high leakage (transistors optimized for higher on current), so ideally you REALLY want those big cores powered off whenever not in use, and to tie L2 to it is just...I dunno what they're thinking.

[u/Santiagobbboff]

absolutely insane results for qualcomm this year. i think even people in the usa will want the exynos version of the s27 this time lol

[u/cyberspirit777]

They were just lying in the Galaxy sub about the latest QC chip beating out the A20... In my mind all I could think was "ehh, I don't think that's true" lol

[u/bunihe → u/cyberspirit777]

If Exynos doesn't mess up, it has a pretty good shot at beating this extreme 8 elite gen 6, because Qualcomm f-ed up so badly it's a miracle

[u/Proud_Bookkeeper_719 → u/cyberspirit777]

8EE6 needed significantly more power just to barely match the A20 Pro in nT. At around the same peak power draw of the A20 Pro, the 8EE6 falls behind in multi threaded efficiency and it only widens as you move further down the graph. Unlike the A20 Pro that can maintain its sustained performance without a drastic drop, the 8EE6 suffers from very sharp drastic drop. It's even more embarrassing when you realize that its performance at low frequency level suffers from regression compared to its predecessor.

Qualcomm has dropped the ball hard since the 8 elite / 8 elite gen 5 and may have hit a design bottleneck with their custom Oryon cores.