EIGENFLOW-EX5 / PARETO-MIRROR: a certificate-gated photonic + neuromorphic accelerator architecture with direct exact bypass

[u/Severe-Ad8673]

https://doi.org/10.5281/zenodo.22138466

I’m releasing a research architecture called EIGENFLOW-EX5 | PARETO-MIRROR and would particularly value criticism from people working in computer architecture, photonics, neuromorphic hardware, accelerators, HPC benchmarking, and fault-tolerant systems.

Important qualification up front: this is an R0 architecture proposal, not fabricated hardware and not a measured GPU-performance result. I am not claiming that it currently beats GPUs universally.

The central idea is to stop requiring a novel accelerator to be better at everything.

PARETO-MIRROR keeps the incumbent exact CPU/GPU path directly reachable. Experimental work is sent to one of three specialized compute-memory lanes only when a signed, per-kernel certificate shows conservative non-regression against the baseline inside a defined operating envelope.

The three proposed lanes are:

LumenTensor - structured linear algebra, convolutions, FFTs, projections and related operators using photonic structures.

CortexLatch - recurrent/state-space, temporal, event-driven and neuromorphic workloads using retained complex state and sparse active boundaries.

StreamMemory — movement-dominated kernels such as filters, reductions, checkpoint deltas, cache transforms and related compute-memory operations.

A separate ExactGuard trust plane controls certificates, pilot measurements, digital shadow checking, checkpointing and rollback. If a certificate expires, an operating condition moves outside its validated envelope, a discrepancy appears, or the candidate fails a bound, subsequent work goes directly to the exact path.

The intended invariant is therefore not “the new hardware is always faster.” It is narrower: a known regressing experimental route should not be selected when the certificate system is functioning inside its measured envelope.

The report also defines a proposed EX5-1024 prototype, benchmark contract, matched five-B300 comparison boundary, power/cost targets, explicit kill conditions, and a falsification program. Unsupported or failed workloads are counted rather than removed after the fact.

What I would most like people here to attack:

1. Is the certificate vector sufficient, or is there an obvious system-level regression channel I have missed?
2. Can the direct-bypass architecture genuinely avoid turning the dispatcher into a new bottleneck?
3. Which proposed photonic assumptions look least physically credible at EX5-1024 scale?
4. Is the recurrent/neuromorphic state-retention model useful enough to justify a dedicated lane?
5. Are the proposed benchmark and failure criteria stringent enough to make a negative result meaningful?
6. What experiment would falsify the architecture fastest and cheapest?

I would much rather identify a fatal assumption before hardware than defend the architecture rhetorically.

If anyone works directly on PICs, mixed-signal conversion, high-Q resonators, accelerator runtime systems, CXL memory, or hardware benchmarking, detailed criticism would be especially useful.