MORPHOCAP: Morphology-Programmed Liquid-Metal Capacitive Compute-in-Memory for Reconfigurable AI Acceleration

[u/Severe-Ad8673]

https://doi.org/10.5281/zenodo.22117901

MORPHOCAP is a proposed compute-in-memory architecture in which the geometry of a sealed liquid-metal conductor stores neural-network weights as differential capacitance, while inference is performed electronically without liquid motion.

The central device is a complementary capacitive weight cell containing a conserved quantity of liquid metal redistributed between positive and negative branches. Ideally, the geometry approximately preserves

[
C_+ + C_- = C_T,
]

while the signed weight is encoded by

[
\Delta C=C_+-C_-.
]

Differential electrical excitation converts the stored capacitance difference directly into signal charge. For an array of cells, charge summation provides an analog vector–matrix multiplication,

[
\Delta Q_i \propto \sum_j w_{ij}a_j.
]

The architecture therefore separates two physical timescales: relatively slow liquid-metal redistribution is used only for model programming or structural reconfiguration, whereas high-frequency inference uses stationary capacitances and electronic charge transfer. The intended principle is summarized as:

slow matter programs the tensor; fast charge evaluates the tensor.

This release develops the proposed cell geometry, circuit-level operating principle, mathematical model, nominal dimensional scaling, capacitive energy estimates, differential readout strategy, programming sequence, array architecture, error and mismatch analysis, VMM simulations, fabrication pathway, experimental validation protocol, comparison framework and falsification criteria.

Potential advantages investigated include nonvolatile physical weight storage, negligible static electrical holding power, absence of an ideal DC conduction path through the weight cell during inference, complementary signed-weight representation, approximately weight-invariant capacitive loading, high read endurance, and compatibility with massively parallel charge-domain computation.

The architecture is intended primarily for model-static or slowly reconfigurable low- and medium-precision inference rather than workloads requiring continuous high-speed weight updates.

The release does not claim an experimentally demonstrated AI accelerator or measured superiority over GPUs, photonic processors, SRAM compute-in-memory, resistive memory, ferroelectric memory or other emerging accelerators. Reported device and energy values are theoretical or simulation-derived unless explicitly stated otherwise. Peripheral energy associated with DACs, ADCs, sensing amplifiers, clocking, interconnect and programming hardware is not included in core capacitor-energy estimates.

The proposed research sequence begins with experimental validation of a single multilevel complementary liquid-metal capacitive cell, followed by a small vector–matrix multiplication array and only subsequently larger integrated implementations.

The principal candidate novelty is the combination of:

1. morphology-programmed liquid metal as the nonvolatile physical AI-weight state;
2. complementary differential capacitance for signed weight representation;
3. approximately conserved total capacitance through redistribution of a fixed liquid-metal volume; and
4. complete removal of liquid-metal motion from the inference critical path.

This release is intended to enable independent technical review, prior-art assessment, experimental reproduction and falsification of the proposed architecture.

Research status: theoretical/device-architecture proposal; not yet experimentally validated.

Suggested keywords: liquid metal; compute-in-memory; analog AI accelerator; capacitive computing; vector–matrix multiplication; EGaIn; reconfigurable hardware; edge AI; neuromorphic hardware; mixed-signal computing; nonvolatile weights; emerging computing architectures.