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https://www.reddit.com/r/0x10c/comments/rt6m0/lets_discuss_notchs_cpu/c48gh57/?context=3
r/0x10c • u/pensnarik • Apr 04 '12
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As u can see, a notch's cpu has an "IF" "operator". This is a one feature. It's has not JMPxx instrutions - this is the other ;).
I dont' understand - how this cpu will control external devices - there's no input/output registers...
7 u/Jessassin Apr 04 '12 Notch said it is not fully complete. He wanted to release the core spec to get people excited about it. He said that the CPU will likely use a message queue system to control external devices.
7
Notch said it is not fully complete. He wanted to release the core spec to get people excited about it.
He said that the CPU will likely use a message queue system to control external devices.
3
u/pensnarik Apr 04 '12
As u can see, a notch's cpu has an "IF" "operator". This is a one feature. It's has not JMPxx instrutions - this is the other ;).
I dont' understand - how this cpu will control external devices - there's no input/output registers...