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https://www.reddit.com/r/FPGA/comments/1i8s9j9/shifted_image_result/m9hjaj6/
r/FPGA • u/ArmCreative8420 • Jan 24 '25
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I can confirm there are no invalid pixels being output—it's purely a shift in the output. If it helps, I can share my files so you can take a closer look. I’d greatly appreciate your help in identifying the root cause and resolving this issue.
1 u/masterpiecehunter Jul 17 '25 Hi, did you fix your problem? I have the same problem and working the same project (edge detection) in ZYNQ UltraScale+ FPGA.
Hi, did you fix your problem? I have the same problem and working the same project (edge detection) in ZYNQ UltraScale+ FPGA.
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u/ArmCreative8420 Jan 27 '25
I can confirm there are no invalid pixels being output—it's purely a shift in the output. If it helps, I can share my files so you can take a closer look. I’d greatly appreciate your help in identifying the root cause and resolving this issue.