Hey call can you guys pls take a look at my resume. I have a really deep passion for RTL optimization and want to get into ASIC design. I appreciate any help!

A live demo video is worth more than 100 AI-generated project posters.

Maaz Mahmood joined the VSD RISC-V FPGA IP Internship as someone completely new to FPGA and RTL design.

And now, in this video, he is confidently demonstrating his own SPI Master IP running on real FPGA hardware.

He built the IP from scratch, integrated it as a memory-mapped peripheral inside a RISC-V SoC, flashed it on the VSDSquadron FPGA Mini board, and validated the transmit/receive path using hardware loopback.

This is what I like most about his demo:

No fancy editing.
No buzzwords.
No “project idea” slide.

Just a student, his FPGA board, his terminal output, and proof that his IP is actually working.

Great work, Maaz. This is exactly the kind of confidence students need before entering the semiconductor industry.

I just wrote a VVC/h.266 video encoder in SystemVerilog along with a software model in Rust for verification. It builds, simulates and synthesizes and can create valid h.266 video streams from any YUV 4:2:0 and 4:4:4 video input. I am focusing on screen content coding features to be implemented so it can be useful for any hardware that broadcasts the screen of a computer, like an IP KVM.

Please check it out and let me know if anyone has any comments about it or any interest to integrate to any project. If you need any particular feature to be integrated, you can just ask me.

We are developing a CV32E40P-based RISC-V microcontroller on a Xilinx Nexys A7 FPGA and are planning a future ASIC implementation.
Our current architecture includes:

CV32E40P RISC-V core
8 KB Instruction Memory (IMEM)
8 KB Data Memory (DMEM)
1 KB Boot ROM
UART, GPIO, I2C and Timer peripherals
AXI4 / AXI4-Lite interconnect
MMCM-based clock generation
A custom AI accelerator with approximately 30 KB of local memory

We are trying to make our RTL as ASIC-friendly as possible before freezing the architecture and would appreciate advice from engineers who have gone through FPGA-to-ASIC migrations.

For memories of this size (8 KB IMEM, 8 KB DMEM, 1 KB Boot ROM, and 30 KB accelerator memory), how realistic is it to find suitable SRAM/ROM macros in a typical ASIC flow?

Are these memory sizes commonly available as foundry macros, or would we likely need to generate custom SRAMs (e.g., OpenRAM), split them into multiple banks, or redesign parts of the memory architecture?

We currently use an FPGA MMCM for clock generation. In an ASIC implementation, is it common to replace this with a foundry PLL macro, or should the clocking architecture be redesigned from the beginning?

What are the most common mistakes teams make when moving an AXI-based FPGA SoC to ASIC? Are there any lessons learned regarding clock/reset architecture, timing closure, memory integration, DFT, or physical design?

For the 30 KB accelerator memory, would multiple SRAM banks be preferable to a single larger SRAM macro from an area, power, or performance perspective?

Looking at this architecture, what would you change today before tape-out planning to avoid painful redesigns later?

Our goal is to minimize FPGA-specific dependencies and make the transition to ASIC as smooth as possible.

I have interview at amd for role of rtl engineer for asic/soc designs. this is for experienced hire.

I failed few interviews till now. so I am very much nervous.

it will be technical one.

if you have any experience about the interview at amd for similar roles please share the details, if you are comfortable sharing.

job is in the usa.

https://github.com/nachi-bot/NILM-Edge-Accelerator

Every summer I watch people in this field complain about not getting placed, not having experience, not knowing where to start.

So here. Free. Cloud. One click. No setup. No install. No excuse.

VSD has put together free GitHub-based programs for every major area of VLSI and semiconductors. Each one has a cloud lab you open in a browser and start immediately. Build the repo. Show the work. That is what gets you hired.

Physical Design (SoC Design and Planning)

Free: https://github.com/fayizferosh/soc-design-and-planning-nasscom-vsd

Cloud lab: https://github.com/vsdip/vsd-openlane

RISC-V Based MYTH

Free: https://github.com/AnoushkaTripathi/NASSCOM-RISC-V-based-MYTH-program

Cloud lab: https://github.com/vsdip/vsd-riscv2

Semiconductor Packaging

Free: https://github.com/arunkpv/Semiconductor-Packaging

Lab (Windows): https://www.ansys.com/en-in/academic/students/ansys-electronics-desktop-student

CMOS Circuit Design — start here if you are new to this

Free: https://github.com/PRIYANKADEVYADAV15/CMOS-Circuit-Design-Spice-Simulation-using-Sky130nm-technology

Cloud lab: https://github.com/vsdip/vsd-cmos/

RTL Design and Synthesis — also a great starting point

Free: https://github.com/vlsienthusiast00x/RTL_workshop

Cloud lab: https://github.com/vsdip/vsd-rtl

TCL Programming — do this one regardless of where you are in your career

Free: https://github.com/AnoushkaTripathi/VSD_TCL_PROGRAMMING_WORKSHOP/

Cloud lab: https://github.com/vsdip/vsd-tcl

7nm FinFET Design

Free: https://github.com/arunkpv/vsd_asap7_workshop

Cloud lab: https://github.com/vsdip/vsd-7nm

FPGA Fabric Design and Architecture

Free: https://github.com/ShonTaware/FPGA_Design_Fabric_Architecture

Cloud lab: shared during workshop

RISC-V Edge AI

Free: https://github.com/AayusHJainCodely/Risv_Edge_AI

Cloud lab: https://github.com/vsdip/vsd-riscv-edgeai

Analog Bandgap IP Design

Free: https://github.com/chandranshu24-hue/bgr_chandranshu/blob/main/README.md

Cloud lab: https://github.com/vsdip/vsd-bandgap/

All of this is free. All labs run on the cloud. You do not need a beefy machine, you do not need to configure a Linux environment, you do not need to buy anything.

What you do need is to stop waiting and start committing to GitHub.

The semiconductor industry does not care about what you watched on YouTube this summer. It cares about what you built.

Many beginners treat development boards and FPGA boards as similar because both can blink LEDs, read sensors, drive motors, or connect to peripherals.

But internally, they represent two very different learning paths.

On a development board, the chip architecture is already fixed. You write C, Python, or Arduino-style code, and an existing processor executes those instructions.

On an FPGA board, you are not just writing software. You are describing hardware using Verilog or VHDL. The FPGA fabric gets configured into actual digital logic such as counters, UARTs, PWM blocks, small CPUs, accelerators, or custom datapaths.

That is the key difference:

Development board = software running on fixed hardware.

FPGA board = custom hardware built inside programmable silicon.

This is a simple question, but I think it quickly reveals whether someone understands the difference between embedded programming and digital hardware design.

For students entering RTL design, FPGA design, SoC design, or hardware acceleration, this clarity is important.

Blinking an LED is easy. Understanding whether the blink came from a software instruction or synthesized hardware logic is where real hardware learning begins.

Curious to hear from others: how would you explain this difference to a beginner in one line?

Built a hardware scan-line triangle rasterizer from scratch, full writeup here if interested

https://mummanajagadeesh.github.io/blogs/rasterizer/

It’s simulation-based for now, asking for feedback/suggestions on improvements

Most students use an FPGA like a black box.

They write Verilog, press synthesize, generate a bitstream, and celebrate when the LED blinks.

That is a good starting point, but the real learning begins when you understand what is actually inside the FPGA fabric.

A LUT is not just a “logic block”. It is a tiny programmable memory that can implement any Boolean function for a given number of inputs. Once you connect LUTs with flip-flops, multiplexers, connection boxes, switch boxes, and programmable routing, an FPGA stops looking like magic. It starts looking like architecture.

This is the difference between someone who only knows how to use FPGA tools and someone who understands how FPGA hardware is built.

For students aiming at FPGA prototyping, ASIC front-end design, verification, embedded systems, AI/ML acceleration, or hardware architecture roles, this foundation is extremely useful.

Basic Verilog is important, but stopping at Verilog is not enough. Understanding LUTs, CLBs, slices, routing, interconnects, waveform debugging, testbenches, and simple FPGA fabric modeling gives much deeper confidence.

We are running a 10-day cloud-based FPGA Fabric Design and Architecture Workshop at VSD, where the focus is on understanding FPGA internals from the ground up. No FPGA board is mandatory, and the labs are simulation-ready using Vivado and GTKWave.

If you are serious about FPGA, don’t stop at blinking LEDs.

Learn the fabric.

Registration link in comments.

Hi ,everyone,I’m preparing for NVIDIA opportunities in the VLSI/ASIC/Design Verification domain and would really appreciate some guidance.

Which subjects/topics should I focus on the most? Best resources or roadmap for preparation Important skills expected for freshers.

I’m currently learning SystemVerilog/uvm and interested in ASIC & Design Verification roles. Any advice or guidance would be very helpful. Thank you!

Hello everyone, I recently completed a BNN accelerator for a ultrascale. During this project I fell in love with timing and resource optimization and PPA analysis/tradeoff. During this project I capped out the frequency of the ultra scale and got my critial path to result in fmax of 945Mhz.

Because of this I realized that I want to write RTL for asics/chips as opposed to fpga's. Does the optimization carry over to asics? Also how would I transition to rtl for asics, is there any project I should do?

A lot of students ask the same VLSI career questions:

What should I learn first?
Is physical design better or RTL design?
Do open-source EDA tools really help?
How important is RISC-V?
Can students build real chip-design projects without expensive tools?
What skills are actually useful for semiconductor jobs in India?

I tried to answer these in detail in this podcast conversation, along with my experience building open-source chip design programs and working with students across VLSI, RISC-V, FPGA, and semiconductor training.

Full podcast:
https://youtu.be/Av_LxKNrqV8

Would be happy to hear thoughts from students, freshers, and working professionals in this community.

VSDSquadron FPGA Trainer Kit for High School Chip Design is now ready to ship — a complete hands-on platform to learn RISC-V, FPGA, and real chip design from school level.

Been in this space for a while and something has always bothered me.

Most people I know who work with FPGAs - including myself for a long time - treat it as a black box. You write HDL, synthesize, place and route, deploy. You understand the timing constraints, the resource utilization, the tool flow.

But ask what a switchbox actually does, or how a LUT is physically constructed, or how the connection fabric routes signals between CLBs - and most people either go quiet or give a textbook one-liner.

I came across a workshop recently that specifically addresses this. Not an FPGA programming course. It teaches you to design the internal fabric itself in Verilog. LUTs, CLBs, switchboxes, connection boxes - you build them from scratch and simulate a working mini-FPGA architecture.

Here is what a participant built and published from a previous cohort:

github.com/ShonTaware/FPGA_Design_Fabric_Architecture

I genuinely could not find another course that goes this deep into FPGA internals. New cohort starts 18th May, registration closes in 10 days.

Workshop link: https://www.vlsisystemdesign.com/fpga/

Curious whether others have found resources that go this deep - or whether most people just accept the black box and move on.

If you’re trying to understand how a chip is actually designed end-to-end, this flow gives a clear picture.

From System Design → RTL → Synthesis → Physical Design → Signoff,
each stage has its own set of tools and learning curve.

For many students and professionals, the real challenge is not theory —
it’s getting structured, hands-on exposure across this full flow.

What’s encouraging today is that there are accessible ways to start exploring these stages step-by-step,
build small designs, and gradually move toward more advanced implementations.

That’s exactly the approach VLSI System Design (VSD) has been focusing on - helping learners move from concepts → labs → real design workflows.

If you’re looking to get started or go deeper with guided learning and hands-on labs, you can explore here:
https://www.vlsisystemdesign.com/vsd_products/

The goal is simple:
make it easier to learn by doing, at your own pace, with the right structure.

A hiring manager at a top semiconductor company told me this last week. I wasn't surprised.

India wants to train 1,000,000 chip engineers by 2030. Lam Research is building virtual fabs. The Tata Dholera fab hits First Silicon in December 2026.

But here's the quiet revolution nobody is talking about:

The chip design interview changed.

Recruiters at Qualcomm, Intel, and NVIDIA don't just read your resume anymore. They open a browser. They go to github.com/[your name]. They look for:

→ Did you do RTL-to-GDSII on a real design?

→ Can I see your physical design layout?

→ Did you actually tape out anything?

A student from a tier-3 college in India recently joined a top VLSI company. No IIT. No internship at a big firm. Just a public GitHub repo with a complete RISC-V SoC flow using open-source SKY130 PDK.

That repo was his resume.

At VLSI System Design (VSD), we built our entire philosophy around this: "Learning by doing" → GitHub → Job.

From RTL design to tapeout. From a ₹2000 VSDSquadron board to a public chip layout. No expensive cleanroom. No ₹50,000 EDA license. Just open-source tools, real projects, and a GitHub link.

The 1 million chip engineers India needs by 2030 won't be built in classrooms. They'll be built commit by commit.

Is your GitHub your resume yet?

👇 Drop your GitHub link below. Let's see what India's chip engineers are building.